Measurement Capability of Laser Ultrasonic Inspection System for Evaluation of Ball-Grid Array Package Solder Balls

Laser ultrasonic inspection is a novel, noncontact, and nondestructive technique to evaluate the quality of solder interconnections in microelectronic packages. In this technique, identification of defects or failures in solder interconnections is performed by comparing the out-of-plane displacement signals, which are produced from the propagation of ultrasonic waves, from a known good reference sample and sample under test. The laboratory-scale dual-fiber array laser ultrasonic inspection system has successfully demonstrated identifying the defects and failures in the solder interconnections in advanced microelectronic packages such as chip-scale packages, plastic ball grid array packages, and flip-chip ball grid array packages. However, the success of any metrology system depends upon precise and accurate data to be useful in the microelectronic industry. This paper has demonstrated the measurement capability of the dual-fiber array laser ultrasonic inspection system using gage repeatability and reproducibility analysis. Industrial flip-chip ball grid array packages have been used for conducting experiments using the laser ultrasonic inspection system and the inspection data are used to perform repeatability and reproducibility analysis. Gage repeatability and reproducibility studies have also been used to choose a known good reference sample for comparing the samples under test.

Correlation Studies Between Laser Ultrasonic Inspection Data and Finite-element Modeling Results in Evaluation of Solder Joint Quality in Microelectronic Packages

Laser Ultrasonic Inspection (LUI) is a non-destructive and non-contact technique to evaluate the quality of solder ball interconnections in area-array microelectronic packages. Dual-Fiber Array Laser Ultrasonic Inspection System was demonstrated identifying defects and failures in chip-scale packages, ball grid array packages, and flip-chip ball grid array packages. The location and severity of the defects and failures in packages have been identified accurately using this system. Further, it is important to establish the correlation between LUI results and the severity of the failures for failure mode analysis, which will enable us to eliminate the need for destructive testing and allow the study of failure evolution in a given sample under continued reliability testing. This paper discusses correlation studies between experimental LUI results and finite-element simulation results from the flip-chip ball grid array packages subjected to thermal cycling reliability testing. The correlation equations will help in predicting the severity of the failures at a given number of thermal cycles based on LUI results. Furthermore, the life of the microelectronic packages can be predicted accurately from LUI results at a fewer number of thermal cycles.

Head-on-Pillow Defect Detection: X-Ray Inspection Limitations

Both the number and the variants of ball grid array packages (BGAs) are tending to increase on network printed board assemblies with sizes ranging from a few millimeter die size wafer level packages with low ball count to large multidie system-in-package (SiP) BGAs with 60–70 mm side lengths and thousands of I/Os. One big challenge, especially for large BGAs, SiPs, and for thin fine-pitch BGA assemblies, is the dynamic warpage during the reflow soldering process. This warpage could lead to solder balls losing contact with the solder paste and its flux during parts of the soldering process, and this may result in solder joints with irregular shapes, indicating poor or no coalescence between the added solder and the BGA balls. This defect is called head-on-pillow (HoP) and is a failure type that is difficult to determine. In this study, x-ray inspection was used as a first step to find deliberately induced HoP defects, followed by prying off of the BGAs to verify real HoP defects and the fault detection correlation between the two methods. The result clearly shows that many of the solder joints classified as potential HoP defects in the x-ray analysis have no evidence at all of HoP after pry-off. This illustrates the difficulty of determining where to draw the line between pass and fail for HoP defects when using x-ray inspection.

Controlling the Solder Joint Reliability of eWLB Packages in Automotive Radar Applications Using a Design for Reliability Approach

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

Experimental Study on 28nm Chip/Package Interactions in eWLB (Embedded Wafer Level BGA) Fan-Out Wafer Level Packages

To meet the continued demand for form factor reduction and functional integration of electronic devices, WLP (Wafer Level Packaging) is an attractive packaging solution with many advantages in comparison with standard BGA (Ball Grid Array) packages. The advancement of fan-out WLP has made it a more promising solution as compared with fan-in WLP, because it can offer greater flexibility in enabling more IO's, multi-chips, heterogeneous integration and 3D SiP. In particular, eWLB (Embedded Wafer Level BGA) is a fan-out WLP solution which can enable applications that require higher I/O density, smaller form factor, excellent heat dissipation, and thin package profile, and it has the potential to evolve in various configurations with proven integration flexibility, process robustness, manufacturing capacity and production yield. It also facilitates integration of multiple dies vertically and horizontally in a single package without using substrates. For eWLB fan-out WLP, the structural design as well as selection of materials is very important in determining the process yield and long term reliability. Therefore it is necessary to investigate the key design factors affecting the reliability comprehensively. This work is focused on an experimental study on the chip-package interactions in eWLB fan-out WLP with multilayer RDL's. Standard JEDEC component and board level tests were carried out to investigate reliability, and both destructive and non-destructive analyses were performed to investigate potential structural defects. Warpage, die cracking and other failures were characterized through metrology measurements and electrical tests. Board assembly processes (including SMT, underfill, etc.) were also studied. The influence of materials and structural design on the package reliability will be demonstrated. Thermal characterization and thermo-mechanical simulation results will also be discussed.