Evaluation of solder joint reliability in flip chip package under thermal shock test

2006 ◽  
Vol 504 (1-2) ◽  
pp. 426-430 ◽  
Author(s):  
Dae-Gon Kim ◽  
Jong-Woong Kim ◽  
Seung-Boo Jung
2009 ◽  
Vol 15 (4) ◽  
pp. 655-660 ◽  
Author(s):  
Sang-Su Ha ◽  
Sang-Ok Ha ◽  
Jeong-Won Yoon ◽  
Jong-Woong Kim ◽  
Min-Kwan Ko ◽  
...  

2014 ◽  
Vol 54 (5) ◽  
pp. 939-944 ◽  
Author(s):  
Ye Tian ◽  
Xi Liu ◽  
Justin Chow ◽  
Yi Ping Wu ◽  
Suresh K. Sitaraman

2018 ◽  
Vol 2018 (1) ◽  
pp. 000104-000109
Author(s):  
Mollie Benson ◽  
Burton Carpenter ◽  
Andrew Mawer

Abstract Radar is currently employed in automotive applications to provide the range, angle, and velocity of objects using RF waves (77GHz). This paper outlines solder joint reliability of a specific micro-processor that processes data received from a SRR (short range radar operating from 0.2 to 30 meters). It is a powerful digital signal processing accelerator, which targets safety applications that require a high Automotive Safety Integrity Level (ASIL-B). The paper explores the package design and construction, SMT (surface mount technology) assembly, and board level reliability testing of various BGA pad surface finish and solder ball alloy materials on a 0.65 mm pitch, 10 × 10 mm body 141 MAPBGA (mold array process-ball grid array) package. The package configurations include two BGA pad surface finishes (Ni/Au and OSP [organic solderability protectant]) and three solder alloys (SnAg, SAC405, and SAC-Bi [a Bi containing SAC derivative]). Solder joint reliability analysis was performed through AATS (air-to-air thermal shock) between 40°C and +125°C and JEDEC Drop Testing at 1500G's. Thermal shock was extended until at least 75% of the populations failed, which was well past the points needed to qualify the packages for the intended end-use applications. The evaluations of the micro-processor indicate that the MAPBGA package can meet the ASIL-B specification requirements with optimized combinations of BGA pad surface finish and solder alloy. The focus of this paper was to determine the baseline solder-joint thermal shock and JEDEC drop performance with varied BGA pad surface finish and solder ball alloy materials.


Author(s):  
Frank Z. Liang ◽  
Rick L. Williams

As electronic package input/output density increases and cost constraints drive the package size smaller, the one area where a designer can not compromise is solder joint reliability. Maintaining flip chip ball grid array (FCBGA) solder joint reliability (SJR) has been at the top of the designer’s critical list with decreasing package size. The FCBGA footprint will need to be modified for a variety of reasons to meet routing optimization, power delivery, electrical performance to name a few. The designer must deal with several competing proposals (electrical performance, cost and use conditions) trying to optimize the FCBGA footprint while being aware that some modifications can negatively affect SJR. This paper investigates solder ball layouts and their effect on SJR through both finite element (FE) models and empirical tests. In addition, consideration of next generation layout is presented to optimize routability while preserving SJR. When feasible, empirical tests were run to validate predictive models.


Sign in / Sign up

Export Citation Format

Share Document