Asymmetric dual-gate tunneling FET with improved performance

Superlattices and Microstructures ◽

10.1016/j.spmi.2016.01.017 ◽

2016 ◽

Vol 91 ◽

pp. 216-224 ◽

Author(s):

Ying Wang ◽

Yan-fu Wang ◽

Wei Xue ◽

Fei Cao

Keyword(s):

Tunneling Fet ◽

Dual Gate ◽

Gate Tunneling ◽

Improved Performance

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Numerical Corrections to Estimate Depletion Region Width in Pseudo-two-dimensional Model of Double-Gate Tunneling FET

10.1109/niles53778.2021.9600561 ◽

2021 ◽

Author(s):

Muhammad Elgamal ◽

Ahmed Shaker

Keyword(s):

Depletion Region ◽

Double Gate ◽

Two Dimensional ◽

Dimensional Model ◽

Tunneling Fet ◽

Two Dimensional Model ◽

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Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

IEEE Transactions on Electron Devices ◽

10.1109/ted.2017.2662580 ◽

2017 ◽

Vol 64 (4) ◽

pp. 1449-1454 ◽

Author(s):

Samia Safa ◽

Samantha Lubaba Noor ◽

Ziaur Rahman Khan

Keyword(s):

Threshold Voltage ◽

Tunneling Fet ◽

Multiple Material ◽

Gate Tunneling ◽

Threshold Voltage Model

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Polarity dependent gate tunneling currents in dual-gate CMOSFETs

IEEE Transactions on Electron Devices ◽

10.1109/16.726656 ◽

1998 ◽

Vol 45 (11) ◽

pp. 2355-2360 ◽

Author(s):

Ying Shi ◽

T.P. Ma ◽

S. Prasad ◽

S. Dhanda

Keyword(s):

Dual Gate ◽

Gate Tunneling ◽

Tunneling Currents

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Analysis of Double Gate Tunneling FET characteristics for low power designs Suppression

2nd International conference on Innovative Engineering Technologies (ICIET'2015) August 7-8, 2015 Bangkok (Thailand) ◽

10.15242/iie.e0815005 ◽

2015 ◽

Keyword(s):

Low Power ◽

Double Gate ◽

Tunneling Fet ◽

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The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Nanoscale Research Letters ◽

10.1186/s11671-018-2483-8 ◽

2018 ◽

Vol 13 (1) ◽

Author(s):

Wei Li ◽

Hongxia Liu ◽

Shulong Wang ◽

Shupeng Chen ◽

Qianqiong Wang

Keyword(s):

Dual Gate ◽

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Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling

AIP Advances ◽

10.1063/1.5087879 ◽

2019 ◽

Vol 9 (4) ◽

pp. 045109 ◽

Author(s):

Wei Li ◽

Hongxia Liu ◽

Shulong Wang ◽

Shupeng Chen ◽

Tao Han ◽

...

Keyword(s):

Dual Gate ◽

On Line ◽

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A Lateral Trench Dual Gate Power MOSFET on Thin SOI for Improved Performance

ECS Journal of Solid State Science and Technology ◽

10.1149/2.021307jss ◽

2013 ◽

Vol 2 (7) ◽

pp. Q113-Q117 ◽

Author(s):

Yashvir Singh ◽

Mayank Punetha

Keyword(s):

Power Mosfet ◽

Dual Gate ◽

Improved Performance

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A Physical Current Model for Multi-Finger Gate Tunneling FET with Schottky Junction

2020 China Semiconductor Technology International Conference (CSTIC) ◽

10.1109/cstic49141.2020.9282442 ◽

2020 ◽

Author(s):

Yimei Li ◽

Jin Luo ◽

Qianqian Huang ◽

Xia An ◽

Le Ye ◽

...

Keyword(s):

Current Model ◽

Schottky Junction ◽

Tunneling Fet ◽

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Double-gate tunneling FET with asymmetric gate structure and pocket source

2014 IEEE International Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2014.7061238 ◽

2014 ◽

Author(s):

Dan Li ◽

Haijun Lou ◽

Xinnan Lin ◽

Lining Zhang ◽

Mansun Chan

Keyword(s):

Double Gate ◽

Tunneling Fet ◽

Gate Structure ◽

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A compact two-dimensional analytical model of the electrical characteristics of a triple-material double-gate tunneling FET structure

Journal of Semiconductors ◽

10.1088/1674-4926/40/12/122901 ◽

2019 ◽

Vol 40 (12) ◽

pp. 122901

Author(s):

C. Usha ◽

P. Vimala

Keyword(s):

Analytical Model ◽

Double Gate ◽

Two Dimensional ◽

Electrical Characteristics ◽

Tunneling Fet ◽

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