scholarly journals Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

2021 ◽  
Vol 183 ◽  
pp. 108125
Author(s):  
Chhandak Mukherjee ◽  
Arnaud Poittevin ◽  
Ian O'Connor ◽  
Guilhem Larrieu ◽  
Cristell Maneux
Silicon ◽  
2021 ◽  
Author(s):  
Girish Shankar Mishra ◽  
N. Mohankumar ◽  
V. Mahesh ◽  
Y. Vamsidhar ◽  
M. Arun Kumar

2021 ◽  
Vol 21 (8) ◽  
pp. 4330-4335
Author(s):  
Jaemin Son ◽  
Doohyeok Lim ◽  
Sangsig Kim

In this study, we examine the electrical characteristics of p+–n+–i–n+ silicon-nanowire field-effect transistors with partially gated channels. The silicon-nanowire field-effect transistors operate with barrier height modulation through positive feedback loops of charge carriers triggered by impact ionization. Our field-effect transistors exhibit outstanding switching characteristics, with an on current of ˜10−4 A, an on/off current ratio of ˜106, and a point subthreshold swing of ˜23 mV/dec. Moreover, the devices inhibit ambipolar characteristics because of the use of the partially gated structure and feature the p-channel operation mode.


2012 ◽  
Vol 70 ◽  
pp. 92-100 ◽  
Author(s):  
Nima Dehdashti Akhavan ◽  
Isabelle Ferain ◽  
Ran Yu ◽  
Pedram Razavi ◽  
Jean-Pierre Colinge

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