Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC

Integration ◽  
2017 ◽  
Vol 59 ◽  
pp. 247-254 ◽  
Author(s):  
Zongwei Li ◽  
Xingyin Xiong ◽  
Xiong Liu ◽  
Kedu Han ◽  
Ning Cong ◽  
...  
Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7280
Author(s):  
Xiangyu Li ◽  
Yangong Zheng ◽  
Xiangyan Kong ◽  
Yupeng Liu ◽  
Danling Tang

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.


2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.


2014 ◽  
Vol 216 ◽  
pp. 43-51 ◽  
Author(s):  
Hesham Omran ◽  
Muhammad Arsalan ◽  
Khaled N. Salama

2011 ◽  
Vol 17 (3) ◽  
pp. 429-436 ◽  
Author(s):  
L. A. Rocha ◽  
R. A. Dias ◽  
E. Cretu ◽  
L. Mol ◽  
R. F. Wolffenbuttel

2014 ◽  
Vol 800-801 ◽  
pp. 741-744
Author(s):  
Zhi Dong Wu ◽  
You Zheng Cui ◽  
Di Pan

In order to meet the demands of the high precision and high speed, the interface design of TMS320C6713 and AD7679 is widely used in data acquisition system. In this paper, the interface design of TMS320C6713 and AD7679 is introduced, including the design of the interface circuit and the software design of the interface. The configuration of every register of McBSP is also expounded, including configuration method and specific function.


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