scholarly journals Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7280
Author(s):  
Xiangyu Li ◽  
Yangong Zheng ◽  
Xiangyan Kong ◽  
Yupeng Liu ◽  
Danling Tang
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
High Signal ◽  
Cmos Process ◽  
Frequency Noise ◽  
Interface Circuit ◽  
Noise Characteristics ◽  
Mems Accelerometers

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

Study of a closed-loop high-precision front-end circuit for tunneling magneto-resistance sensors

2019 ◽  
Vol 33 (08) ◽  
pp. 1950085 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Corner Frequency ◽  
Cmos Process ◽  
Interface Circuit ◽  
Front End ◽  
Magneto Resistance

A closed-loop high-precision front-end interface circuit in a standard 0.35 [Formula: see text]m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 [Formula: see text]m CMOS process and the active circuit area is about [Formula: see text]. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of [Formula: see text]. The ripple can be suppressed to less than 10 [Formula: see text]V by ripple suppression loop.

A speed-optimized, low-noise APD with 0.18 μm CMOS technology for the VLC applications

2020 ◽  
Vol 34 (29) ◽  
pp. 2050321
Author(s):  
Wei Wang ◽  
Hong-An Zeng ◽  
Fang Wang ◽  
Guanyu Wang ◽  
Yingtao Xie ◽  
...  
Keyword(s):  
Dark Current ◽  
Complementary Metal Oxide Semiconductor ◽  
Visible Light Communication ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Excess Noise ◽  
Avalanche Breakdown ◽  
Cmos Process ◽  
Noise Characteristics

A new avalanche photodiode device applied to a visible light communication (VLC) system is designed using a standard 0.18 [Formula: see text]m complementary metal oxide semiconductor process. Compared to regular CMOS APD devices, the proposed device adds a [Formula: see text]-well layer above the deep [Formula: see text]-well/[Formula: see text]-substrate structure, and an [Formula: see text]/[Formula: see text] layer is deposited upon it. The [Formula: see text]/[Formula: see text] layer acts as an avalanche breakdown layer of the device, and an STI structure is used to prevent the edge break prematurely. The simulation results shows that the avalanche breakdown voltage is as low as 9.9 V, dark current is below [Formula: see text] A under −9.5 V bias voltage, and the 3 dB bandwidth is of 5.9 GHz. It is due to the use of the 0.18 [Formula: see text]m CMOS process-specific STI protection ring and short-circuits the connection of the deep [Formula: see text]-well/[Formula: see text]-substrate, and the dark current is reduced to be lower than two orders of magnitude compared to regular CMOS APD. Gain and noise characteristics are accurately calculated from Hayat dead-space model applied to this CMOS APD. So, this device’s gain and excess noise factor are 20 and 2.5, respectively.

scholarly journals A High-Temperature, Low-Noise Readout ASIC for MEMS-Based Accelerometers

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 241 ◽  
Author(s):  
Min Qi ◽  
An-qiang Guo ◽  
Dong-hai Qiao
Keyword(s):  
Integrated Circuit ◽  
Sampling Technique ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Frequency Noise ◽  
Voltage Reference ◽  
Noise Floor ◽  
Mems Sensor ◽  
Output Noise

This paper presents the development and measurement results of a complementary metal oxide semiconductor (CMOS) readout application-specific integrated circuit (ASIC) for bulk-silicon microelectromechanical system (MEMS) accelerometers. The proposed ASIC converts the capacitance difference of the MEMS sensor into an analog voltage signal and outputs the analog signal with a buffer. The ASIC includes a switched-capacitor analog front-end (AFE) circuit, a low-noise voltage reference generator, and a multi-phase clock generator. The correlated double sampling technique was used in the AFE circuits to minimize the low-frequency noise of the ASIC. A programmable capacitor array was implemented to compensate for the capacitance offset of the MEMS sensor. The ASIC was developed with a 0.18 μm CMOS process. The test results show that the output noise floor of the low-noise amplifier was −150 dBV/√Hz at 100 Hz and 175 °C, and the sensitivity of the AFE was 750 mV/pF at 175 °C. The output noise floor of the voltage reference at 175 °C was −133 dBV/√Hz at 10 Hz and −152 dBV/√Hz at 100 Hz.

scholarly journals Low-Noise Multimodal Reconfigurable Sensor Readout Circuit for Voltage/Current/Resistive/Capacitive Microsensors

2020 ◽  
Vol 10 (1) ◽  
pp. 348 ◽  
Author(s):  
Donggeun You ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
Low Noise ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Frequency Noise ◽  
Readout Circuit ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chopper Stabilization ◽  
Total Power Consumption

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm2. The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µVrms from 1 Hz to 200 Hz.

scholarly journals A Four-Channel Low-Noise Readout IC for Air Flow Measurement Using Hot Wire Anemometer in 0.18 μm CMOS Technology

Sensors ◽  
2021 ◽  
Vol 21 (14) ◽  
pp. 4694
Author(s):  
Kyeongsik Nam ◽  
Hyungseup Kim ◽  
Yongsu Kwon ◽  
Gyuri Choi ◽  
Taeyup Kim ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Air Flow ◽  
Low Noise ◽  
Cmos Process ◽  
Significant Information ◽  
Flow Measurements ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Op Amp ◽  
Noise Characteristics

Air flow measurements provide significant information required for understanding the characteristics of insect movement. This study proposes a four-channel low-noise readout integrated circuit (IC) in order to measure air flow (air velocity), which can be beneficial to insect biomimetic robot systems that have been studied recently. Instrumentation amplifiers (IAs) with low-noise characteristics in readout ICs are essential because the air flow of an insect’s movement, which is electrically converted using a microelectromechanical systems (MEMS) sensor, generally produces a small signal. The fundamental architecture employed in the readout IC is a three op amp IA, and it accomplishes low-noise characteristics by chopping. Moreover, the readout IC has a four-channel input structure and implements an automatic offset calibration loop (AOCL) for input offset correction. The AOCL based on the binary search logic adjusts the output offset by controlling the input voltage bias generated by the R-2R digital-to-analog converter (DAC). The electrically converted air flow signal is amplified using a three op amp IA, which is passed through a low-pass filter (LPF) for ripple rejection that is generated by chopping, and converted to a digital code by a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). Furthermore, the readout IC contains a low-dropout (LDO) regulator that enables the supply voltage to drive digital circuits, and a serial peripheral interface (SPI) for digital communication. The readout IC is designed with a 0.18 μm CMOS process and the current consumption is 1.886 mA at 3.3 V supply voltage. The IC has an active area of 6.78 mm2 and input-referred noise (IRN) characteristics of 95.4 nV/√Hz at 1 Hz.

Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC

Integration ◽  
2017 ◽  
Vol 59 ◽  
pp. 247-254 ◽  
Author(s):  
Zongwei Li ◽  
Xingyin Xiong ◽  
Xiong Liu ◽  
Kedu Han ◽  
Ning Cong ◽  
...  
Keyword(s):  
High Precision ◽  
Floating Point ◽  
Digital Interface ◽  
Interface Circuit ◽  
Mems Accelerometers ◽  
Capacitive Mems

scholarly journals A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2726
Author(s):  
Xiangwei Zhang ◽  
Quan Li ◽  
Chengying Chen ◽  
Yan Li ◽  
Fuqiang Zuo ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Field Potential ◽  
Low Noise ◽  
Recording System ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Neural Signals ◽  
Fully Integrated ◽  
Rail To Rail

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

scholarly journals Low-Noise Chopper-Stabilized Multi-Path Operational Amplifier with Nested Miller Compensation for High-Precision Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 281 ◽  
Author(s):  
Jaesung Kim ◽  
Hyungseup Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
Hyunwoo Heo ◽  
...  
Keyword(s):  
High Precision ◽  
Operational Amplifier ◽  
High Frequency ◽  
Flicker Noise ◽  
Low Frequency ◽  
Low Noise ◽  
Cmos Process ◽  
Miller Compensation ◽  
Chopper Stabilization ◽  
Nested Miller Compensation

This paper presents a low-noise multi-path operational amplifier for high-precision sensors. A chopper stabilization technique is applied to the amplifier to remove offset and flicker noise. A ripple reduction loop (RRL) is designed to remove the ripple generated in the process of up-modulating the flicker noise and offset. To cancel the notch in the overall transfer function due to the RRL operation, a multi-path architecture using both a low-frequency path (LFP) and high-frequency path (HFP) is implemented. The low frequency path amplifier is implemented using the chopper technique and the RRL. In the high-frequency path amplifier, a class-AB output stage is implemented to improve the power efficiency. The transfer functions of the LFP and HFP induce a first-order frequency response in the system through nested Miller compensation. The low-noise multi-path amplifier was fabricated using a 0.18 µm 1P6M complementary metal-oxide-semiconductor (CMOS) process. The power consumption of the proposed low-noise operational amplifier is 0.174 mW with a 1.8 V supply and an active area of 1.18 mm2. The proposed low-noise amplifier has a unit gain bandwidth (UGBW) of 3.16 MHz, an input referred noise of 11.8 nV/√Hz, and a noise efficiency factor (NEF) of 4.46.

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