scholarly journals Low-Temperature Electroluminescence Excitation Mapping of Excitons and Trions in Short-Channel Monochiral Carbon Nanotube Devices

ACS Nano ◽  
2020 ◽  
Vol 14 (3) ◽  
pp. 2709-2717 ◽  
Author(s):  
Marco Gaulke ◽  
Alexander Janissek ◽  
Naga Anirudh Peyyety ◽  
Imtiaz Alamgir ◽  
Adnan Riaz ◽  
...  

2020 ◽  
Vol MA2020-01 (7) ◽  
pp. 671-671
Author(s):  
Marco Gaulke ◽  
Naga Anirudh Peyyety ◽  
Imtiaz Alamgir ◽  
Adnan Riaz ◽  
Simone Dehm ◽  
...  


ACS Nano ◽  
2010 ◽  
Vol 4 (5) ◽  
pp. 2659-2666 ◽  
Author(s):  
Paul Stokes ◽  
Saiful I. Khondaker


2021 ◽  
Vol 118 (6) ◽  
pp. 063101
Author(s):  
Alexander Janissek ◽  
Jakob Lenz ◽  
Fabio del Giudice ◽  
Marco Gaulke ◽  
Felix Pyatkov ◽  
...  


2014 ◽  
Vol 21 (6) ◽  
pp. 1225-1231
Author(s):  
KyungNam Kang ◽  
Jeonghwan Kim ◽  
Yoonyoung Jin ◽  
Pratul K. Ajmera


1995 ◽  
Vol 06 (02) ◽  
pp. 317-373 ◽  
Author(s):  
G. GILDENBLAT ◽  
D. FOTY

We review the modeling of silicon MOS devices in the 10–300 K temperature range with an emphasis on the specifics of low-temperature operation. Recently developed one-dimensional models of long-channel transistors are discussed in connection with experimental determination and verification of the effective channel mobility in a wide temperature range. We also present analytical pseudo-two-dimensional models of short-channel devices which have been proposed for potential use in circuit simulators. Several one-, two-, and three-dimensional numerical models are discussed in order to gain insight into the more subtle details of the low-temperature device physics of MOS transistors and capacitors. Particular attention is paid to freezeout effects which, depending on the device design and the ambient temperature range, may or may not be important for actual device operation. The numerical models are applied to study the characteristic time scale of freezeout transients in the space-charge regions of silicon devices, to the analysis and suppression of delayed turn-off in MOS transistors with compensated channel, and to the temperature dependence of three-dimensional effects in short-channel, narrow-channel MOSFETs.



2017 ◽  
Vol 4 (18) ◽  
pp. 1700238 ◽  
Author(s):  
Hameeda Jagalur Basheer ◽  
Charlotte Pachot ◽  
Ugo Lafont ◽  
Xavier Devaux ◽  
Naoufal Bahlawane




Adder Is Basic Unit For Any Digital System, Dsp And Microprocessor. The Main Issue In Design High Speed Full Adder Cell With The Low Power Dissipation. As We Know Cmos Technology Used For Vlsi Designing Cmos Has Many Drawbacks As High Power Short Channel Effect Etc. Then Cntfet (Carbon Nanotube Field Effect Transistor) Has Been Developed Which Has Same Structure As Cmos. The Difference Between Structure Of Cmos And Cntfet Is Their Channel. In Cntfet Channel Is Replaced By Carbon Nanotube. In This Paper We Compare Full Adder Circuit Using Cntfet With Gdi Technique And Cmos Implementation Of Adder Which Gdi Technique. Gdi Technique Is Used For Speed And Power Optimization In Digital Circuit. This Can Also Reduce The Count Of Transistor Which Affects The Size Of Device.



2011 ◽  
Vol 23 (47) ◽  
pp. 475302 ◽  
Author(s):  
M Salvato ◽  
M Lucci ◽  
I Ottaviani ◽  
M Cirillo ◽  
S Orlanducci ◽  
...  


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