An Ultra-Low Power MOS2 Tunnel Field Effect Transistor PLL Design for IoT Applications

2021 ◽  
Author(s):  
Naheem Olakunle Adesina ◽  
Ashok Srivastava ◽  
Azmot Ullah Khan ◽  
Jian Xu
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ultra Low Power ◽  
Iot Applications ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Optimal design for a high performance H-JLTFET using HfO2 as a gate dielectric for ultra low power applications

RSC Advances ◽  
2014 ◽  
Vol 4 (43) ◽  
pp. 22803-22807 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Bahniman Ghosh ◽  
Shiromani Bal Mukund Rahi ◽  
Yogesh Goswami
Keyword(s):  
Optimal Design ◽  
Low Power ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
Gate Dielectric ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor using HfO2 as a gate dielectric.

Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications

RSC Advances ◽  
2015 ◽  
Vol 5 (60) ◽  
pp. 48779-48785 ◽  
Author(s):  
Pranav Kumar Asthana ◽  
Yogesh Goswami ◽  
Shibir Basak ◽  
Shiromani Balmukund Rahi ◽  
Bahniman Ghosh
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ultra Low Power ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Improved Performance

In this paper, we present improved device characteristics of a Junctionless Tunnel Field Effect Transistor (JLTFET) with a Si and SiGe heterostructure.

Sign in / Sign up

Export Citation Format

Share Document