Ultra-low power Hf0.5Zr0.5O2 based ferroelectric tunnel junction synapses for hardware neural network applications

Nanoscale ◽  
2018 ◽  
Vol 10 (33) ◽  
pp. 15826-15833 ◽  
Author(s):  
Lin Chen ◽  
Tian-Yu Wang ◽  
Ya-Wei Dai ◽  
Ming-Yang Cha ◽  
Hao Zhu ◽  
...  
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Tunnel Junction ◽  
Boolean Logic ◽  
Great Promise ◽  
Ultra Low Power ◽  
Network Applications ◽  
Ferroelectric Tunnel Junction ◽  
Neural Network Applications ◽  
Hardware Neural Network

Brain-inspired neuromorphic computing has shown great promise beyond the conventional Boolean logic.

CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications

2021 ◽  
pp. 1-6
Author(s):  
Yi-Shan Kuo ◽  
Shen-Yang Lee ◽  
Chia-Chin Lee ◽  
Shou-Wei Li ◽  
Tien-Sheng Chao
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Tunnel Junction ◽  
Network Applications ◽  
Cmos Compatible ◽  
Ferroelectric Tunnel Junction ◽  
Neural Network Applications

multiPULPly

2021 ◽  
Vol 17 (2) ◽  
pp. 1-27
Author(s):  
Adi Eliahu ◽  
Ronny Ronen ◽  
Pierre-Emmanuel Gaillardon ◽  
Shahar Kvatinsky
Keyword(s):  
Neural Network ◽  
Power Consumption ◽  
Power Systems ◽  
Low Power ◽  
Network Inference ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Network Applications ◽  
Low Power Cmos ◽  
Neural Network Applications

Computationally intensive neural network applications often need to run on resource-limited low-power devices. Numerous hardware accelerators have been developed to speed up the performance of neural network applications and reduce power consumption; however, most focus on data centers and full-fledged systems. Acceleration in ultra-low-power systems has been only partially addressed. In this article, we present multiPULPly, an accelerator that integrates memristive technologies within standard low-power CMOS technology, to accelerate multiplication in neural network inference on ultra-low-power systems. This accelerator was designated for PULP, an open-source microcontroller system that uses low-power RISC-V processors. Memristors were integrated into the accelerator to enable power consumption only when the memory is active, to continue the task with no context-restoring overhead, and to enable highly parallel analog multiplication. To reduce the energy consumption, we propose novel dataflows that handle common multiplication scenarios and are tailored for our architecture. The accelerator was tested on FPGA and achieved a peak energy efficiency of 19.5 TOPS/W, outperforming state-of-the-art accelerators by 1.5× to 4.5×.

Design of a Low Power Bfloat16 Pipelined MAC Unit for Deep Neural Network Applications

2021 ◽  
Author(s):  
Ankita Tiwari ◽  
Gaurav Trivedi ◽  
Prithwijit Guha
Keyword(s):  
Neural Network ◽  
Low Power ◽  
Deep Neural Network ◽  
Network Applications ◽  
Neural Network Applications

3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications

2016 ◽  
Vol 27 (36) ◽  
pp. 365204 ◽  
Author(s):  
I-Ting Wang ◽  
Chih-Cheng Chang ◽  
Li-Wen Chiu ◽  
Teyuh Chou ◽  
Tuo-Hung Hou
Keyword(s):  
Neural Network ◽  
Network Applications ◽  
Neural Network Applications ◽  
Hardware Neural Network
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