Analogue IC Design: the Current Mode Approach

1992 ◽  
Vol 4 (3) ◽  
pp. 151
Author(s):  
G. Pearce
Keyword(s):  
IEE Review ◽  
1991 ◽  
Vol 37 (1) ◽  
pp. 33 ◽  
Author(s):  
J.K. Fidler
Keyword(s):  

1990 ◽  
Vol 137 (2) ◽  
pp. 61 ◽  
Author(s):  
Chris Toumazou ◽  
John Lidgey ◽  
Brett Wilson

2018 ◽  
Vol 138 (5) ◽  
pp. 453-462
Author(s):  
Jun-ichi Itoh ◽  
Tomokazu Sakuraba ◽  
Hoai Nam Le ◽  
Hiroki Watanabe ◽  
Keisuke Kusaka

Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.


Author(s):  
Steve Ferrier ◽  
Kevin D. Martin ◽  
Donald Schulte

Abstract Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.


2020 ◽  
Vol 10 (6) ◽  
pp. 902-908
Author(s):  
Syed Zahiruddin ◽  
Avireni Srinivasulu ◽  
Musala Sarada

Objective: The interest concern towards the development of enabling technology towards new current mode devices has forced the designers and researchers for the invention of devices, which has having the characteristics like such as low power, robustness, compactness, efficiency and scalability. Methods: Second Generation Current Controlled Conveyor (CCCII) is the prevailing current mode device of the times today. Since its invention by A. Fabre, it has prominent applications in the field of analog signal processing and in biomedical applications too. In this manuscript, CCCII is used as an enabling device to design a Frequency Shift Keying (FSK) Generator. Results: The proposed topology is designed using a single active device CCCII with least passive components. The circuit enjoys the features of like electronic tunability of frequency using the bias current. Conclusion: It can be concluded that the FSK generator circuit designed using single CCCII confers better results in contrast to the existing structures. The maximum power consumption is 0.196 mW. The proposed circuit has the benefit of simple configuration, which is very much proficient for IC fabrication.


Sign in / Sign up

Export Citation Format

Share Document