Contributions of a Formal Analysis Metaprocess to Breakthrough Failure Analysis Results

Author(s):  
Steve Ferrier ◽  
Kevin D. Martin ◽  
Donald Schulte

Abstract Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.

Author(s):  
Todd M. Simons ◽  
Bob Davis

Abstract Photon emission microscopy (PEM) provides a valuable first step in the failure analysis process. An analysis of a mixed signal bipolar/CMOS silicon on insulator (SOI) device revealed an abnormal emission site that appeared to emanate from the oxide isolation ring. Subsequent mechanical probing of the emitting bipolar transistor revealed node voltages nearly identical to a known good reference unit that had no emission site at the affected transistor. This article analyzes the reasons for the emission site on one transistor and not the other even though the node voltages were the same. It was observed that while the node voltages were nearly identical, the available current paths were not. The different paths directly related to the amount of available carriers for recombination in the base. The construction of the SOI device creates unique optical paths for emission sites not observed in non-SOI devices. It can be concluded that the failure mechanism does not always reside at the abnormal PEM site.


Author(s):  
C.Q. Chen ◽  
Z.H. Mai ◽  
G.B. Ang ◽  
B.H. Liu ◽  
P.T. Ng ◽  
...  

Abstract As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.


Author(s):  
Z. G. Song ◽  
S. B. Ippolito ◽  
P. J. McGinnis ◽  
A. Shore ◽  
B. Paulucci ◽  
...  

Abstract It is generally accepted that the fault isolation of Vdd short and leakage can be globally addressed by liquid crystal analysis (LCA), photoemission analysis and/or laser stimulating techniques such as OBIRCH or TIVA. However, the hot spot detected by these techniques may be a secondary effect, rather than the exact physical defect location. Further electrical probing with knowledge of the circuit schematic and layout may still be required to pinpoint the exact physical defect location, so that a suitable physical analysis methodology can be chosen to identify the root cause of the failure. This paper has described a thorough analysis process for Vdd leakage failure by a combination of various failure analysis techniques and finally the root cause of the Vdd leakage was identified.


Author(s):  
Kuo Hsiung Chen ◽  
Wen Sheng Wu ◽  
Yu Hsiang Shu ◽  
Jian Chan Lin

Abstract IR-OBIRCH (Infrared Ray – Optical Beam Induced Resistance Change) is one of the main failure analysis techniques [1] [2] [3] [4]. It is a useful tool to do fault localization on leakage failure cases such as poor Via or contact connection, FEoL or BEoL pattern bridge, and etc. But the real failure sites associated with the above failure mechanisms are not always found at the OBIRCH spot locations. Sometimes the real failure site is far away from the OBIRCH spot and it will result in inconclusive PFA Analysis. Finding the real failure site is what matters the most for fault localization detection. In this paper, we will introduce one case using deep sub-micron process generation which suffers serious high Isb current at wafer donut region. In this case study a BEoL Via poor connection is found far away from the OBIRCH spots. This implies that layout tracing skill and relation investigation among OBIRCH spots are needed for successful failure analysis.


Author(s):  
I. Österreicher ◽  
S. Eckl ◽  
B. Tippelt ◽  
S. Döring ◽  
R. Prang ◽  
...  

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.


Author(s):  
Sarven Ipek ◽  
David Grosjean

Abstract The application of an individual failure analysis technique rarely provides the failure mechanism. More typically, the results of numerous techniques need to be combined and considered to locate and verify the correct failure mechanism. This paper describes a particular case in which different microscopy techniques (photon emission, laser signal injection, and current imaging) gave clues to the problem, which then needed to be combined with manual probing and a thorough understanding of the circuit to locate the defect. By combining probing of that circuit block with the mapping and emission results, the authors were able to understand the photon emission spots and the laser signal injection microscopy (LSIM) signatures to be effects of the defect. It also helped them narrow down the search for the defect so that LSIM on a small part of the circuit could lead to the actual defect.


Author(s):  
H.H. Yap ◽  
P.K. Tan ◽  
G.R. Low ◽  
M.K. Dawood ◽  
H. Feng ◽  
...  

Abstract With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.


Author(s):  
Thierry Parrassin ◽  
Sylvain Dudit ◽  
Michel Vallet ◽  
Antoine Reverdy ◽  
Hervé Deslandes

Abstract By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.


Author(s):  
Mehrdad Mahanpour ◽  
Andy Gray ◽  
Jose Hulog ◽  
Pat Chang

Abstract C4 (Controlled Collapse Chip Connection) failure analysis compared to conventional packages (DIP- LCC- QFP, etc.) is not trivial. For instance, one has to thin the C4 die for IR microscope inspection or for photon emission analysis. Then, after failure analysis on the die, it must be removed for deprocessing or further analysis. Three methods and techniques will be discussed for removing the C4 die from the package without damaging the die. However, for each technique it is very important to know the condition of the die and package prior to die removal. The method used will differ, for example, if the die is thinned or not.


2018 ◽  
Vol 10 (8) ◽  
pp. 168781401879410 ◽  
Author(s):  
Yahui Cui ◽  
Jing Gao ◽  
Xiaomin Ji ◽  
Xintao Zhou ◽  
Haitao Yan

The concept of multi-attribute topological graph is proposed in this article to represent the characteristics of both structure and state for typical one-degree-of-freedom planar spur closed planetary gear trains. This method is well applied in power flow analysis and provides a graphical view for the types, values, directions, and transmission relationship of power flow, especially for the recirculation power representation. Furthermore, a template model of multi-attribute topological graph for closed planetary gear trains is also presented, which would be helpful to the multi-attribute topological graph generation for some certain types of closed planetary gear trains just by changing symbols in the template model. A corresponding software is also developed to make the analysis process more convenient. By inputting different parameters, the different visual results can be obtained automatically, thus benefiting engineers in conceptual design.


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