With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.
An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing