Design of Micro Power Consumption Synchronous Chopped Wave Power Supply Based on Fixed and Mobile Double Comparative Point

2014 ◽  
Vol 986-987 ◽  
pp. 1794-1798
Author(s):  
Long Teng Wang ◽  
Jun Lin ◽  
Hui Su
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Output Voltage ◽  
Low Voltage ◽  
Design Method ◽  
Short Circuit ◽  
Maximum Output ◽  
Residual Voltage ◽  
Micro Power

This paper proposes a design method of the micro power consumption synchronous chopped wave and low-power switching power supply based on fixed and mobile double comparative point. The output of this power supply ranges from 5V to 200V. It overcomes the residual voltage effect after the bridge rectifier by using fixed comparative point to limit the maximum output voltage, and stabilizes the voltage by using mobile point to produce the required output voltage. The circuit charges with nonlinear resistors pattern in the low voltage, thus improving the charging efficiency, and it has short circuit protection function, simple structure and low power consumption.

Design of a piezoelectric energy conversion based wind generator

2021 ◽  
pp. 002072092110134
Author(s):  
Sibel Akkaya Oy ◽  
Ali Ekber Özdemir
Keyword(s):  
Low Power ◽  
Energy Conversion ◽  
Output Voltage ◽  
Sensor Nodes ◽  
Maximum Output ◽  
Wireless Sensor Nodes ◽  
Wind Speeds ◽  
Wind Generator ◽  
Piezoelectric Energy ◽  
Renewable Energy Generation

This manuscript presents a new experimental wind generator based on piezoelectric energy conversion for low power applications. The aim is to demonstrate an alternative renewable energy generation method for low power applications. The generator has four blades of a propeller equipped with a total of twenty-four (24) thin film piezoelectric transducers (TFPTs). The output voltage is generated using a newly developed circuit topology. The generator was tested at three wind speeds 10 m/s, 14 m/s and 18 m/s, with a maximum output voltage of 10.2 V being produced at a wind speed of 18 m/s. Results show that this generator has promise to be suitable for low power batteryless applications, for example wireless sensor nodes (WSN).

Micro-Power Wireless CSMA/CA Algorithm Improvement and Simulation Based on the Electric Power Business

2014 ◽  
Vol 494-495 ◽  
pp. 1640-1646
Author(s):  
Yu Lan ◽  
Xin Lu ◽  
Ye Shen He ◽  
Yun Feng Li
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Collision Detection ◽  
Wireless Transmission ◽  
Low Power Consumption ◽  
Mac Layer ◽  
Electric System ◽  
Simulation Based ◽  
Micro Power ◽  
Fixed Power

In the micro-power wireless transmission of the electric system, positions among modes are relatively fixed, power business data is reported at specific time points, and time distribution presents great differences. Key technologies of IEEE802.15.4 MAC layer protocol is expounded, shortages of collision detection and CSMA/CA on power business support, etc. are discussed, self-adaptive low-power consumption CSMA/CA algorithm which is more suitable for business of the electric system are designed and improved, and the algorithm goes through simulation experiment against the business characteristics of micro-power wireless network of the electric system. The simulation result demonstrates the algorithm may be greatly adapted to changes of network traffic under a relatively fixed environment of network topology on the premise of low power consumption.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A LOW-POWER UWB TRANSCEIVER BY USE OF TRIGGER RECEIVING METHOD

2010 ◽  
Vol 19 (07) ◽  
pp. 1609-1619 ◽  
Author(s):  
SHENG ZHANG ◽  
ZHENG LI ◽  
MENGMENG LIU ◽  
XIAOKANG LIN
Keyword(s):  
Energy Consumption ◽  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Circuit Complexity ◽  
Cmos Process ◽  
Fully Integrated

This paper presents a novel non-coherent receiving algorithm termed trigger receiving algorithm. In comparison with conventional coherent receiving method, the trigger receiving algorithm needs neither local template nor correlation operation, thus both circuit complexity and power consumption are drastically reduced. Based on the proposed algorithm, a fully integrated transceiver was implemented in a 0.18 μ m CMOS process. It occupies an area of 0.44 mm2 and achieves a maximum chip rate of 40 Mbps with 7 mW energy consumption provided by a 1.8 V power supply.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

Low Power Electronics for Square-Wave Piezoactuator Driving

2009 ◽  
Author(s):  
G. Biancuzzi ◽  
T. Lemke ◽  
F. Goldschmidtboeing ◽  
O. Ruthmann ◽  
H.-J. Schrag ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Converter ◽  
Driving Voltage ◽  
Output Stage ◽  
Maximum Displacement ◽  
Artificial Sphincter ◽  
Charge Recovery

The German Artificial Sphincter System (GASS) project aims at the development of an implantable sphincter prosthesis driven by a micropump. During the last few years the feasibility of the concept has been proven. At present our team’s effort is focused on the compliance to safety regulations and on a very low power consumption of the system as a whole. Therefore a low-voltage multilayer piezoactuator has been developed to reduce the driving voltage of the micropump from approximately 300 Vpp to 40 Vpp. Doing so, the driving voltage is within the limits set by the regulations for active implants. The operation of the micropump at lower voltages, achieved using multilayer piezoactuators, has already resulted in a much better power efficiency. Nevertheless, in order to further reduce power consumption, we have also developed an innovative driving technique that we are going to describe and compare to other driving systems. A direct switching circuit has been developed where the buffer capacitor of the step-up converter has been replaced by the equivalent capacitance of the actuator itself. This avoids the switching of the buffer capacitor to the actuator, which would result in a very low efficiency. Usually, a piezoactuator needs a bipolar voltage drive to achieve maximum displacement. In our concept, the voltage inversion across the actuator is done using an h-bridge circuit, allowing the employment of one step-up converter only. The charge stored in the actuator is then partially recovered by means of a step-down converter which stores back the energy at the battery voltage level. The power consumption measurements of our concept are compared to a conventional driving output stage and also with inductive charge recovery circuits. In particular, the main advantage, compared to the latter systems, consists in the small inductors needed for the power converter. Other charge recovery techniques require very big inductors in order to have a significant power reduction with the capacitive loads we use in our application. With our design we will be able to achieve approximately 55% reduction in power consumption compared to the simplest conventional driver and 15% reduction compared to a charge recovery driver.

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