SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays

2009 ◽  
Vol 3 (1) ◽  
pp. 24 ◽  
Author(s):  
I.D.L. Anderson ◽  
M.A.S. Khalid
Keyword(s):  
Computer Aided Design ◽  
Design Space Exploration ◽  
Design Space ◽  
Design Tool ◽  
Processing Unit ◽  
Central Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Aided Design

scholarly journals Implementation of Leakage Power Reduction Techniques in Field Programmable Device

2019 ◽  
Vol 9 (2) ◽  
pp. 5115-5123
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
System Level ◽  
Gate Arrays ◽  
Reduction Techniques ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays ◽  
Power And Energy ◽  
Aided Design

This paper provide a summary of low-power technique for field-programmable gate arrays (FPDs). It cover system level propose technique as well as device level propose methods that have besieged present trade devices. In addition to describe present investigate happening circuit level as well as architecture-level create technique. Current studies on power model as well as on low-power computer-aided design (CAD) are also information. At last, it proposes that would allow the use of Field Programmable Device (FPD) equipment in applications where power and energy consumption is critical, such as mobile devices.

Approaches for FPGA Design Assurance

2022 ◽  
Vol 15 (3) ◽  
pp. 1-29
Author(s):  
Eli Cahill ◽  
Brad Hutchings ◽  
Jeffrey Goeders
Keyword(s):  
Computer Aided Design ◽  
Fpga Design ◽  
Gate Arrays ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Custom Hardware ◽  
Aided Design ◽  
Closed Source ◽  
Complex Computer

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

scholarly journals Real-Time Monte Carlo Optimization on FPGA for the Efficient and Reliable Message Chain Structure

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 866 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim
Keyword(s):  
Monte Carlo ◽  
Real Time ◽  
Communication Systems ◽  
Optimization Method ◽  
Chain Structure ◽  
Processing Unit ◽  
Monte Carlo Optimization ◽  
Central Processing ◽  
Field Programmable ◽  
Programmable Gate Arrays

This paper addresses the real-time optimization problem to find the most efficient and reliable message chain structure in data communications based on half-duplex command–response protocols such as MIL-STD-1553B communication systems. This paper proposes a real-time Monte Carlo optimization method implemented on field programmable gate arrays (FPGA) which can not only be conducted very quickly but also avoid the conflicts with other tasks on a central processing unit (CPU). Evaluation results showed that the proposed method can consistently find the optimal message chain structure within a quite small and deterministic time, which was much faster than the conventional Monte Carlo optimization method on a CPU.

scholarly journals FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip

2018 ◽  
Vol 7 (2.16) ◽  
pp. 57
Author(s):  
G Prasad Acharya ◽  
M Asha Rani
Keyword(s):  
Computer Aided Design ◽  
Processing System ◽  
System On Chip ◽  
Core System ◽  
Design Cycle ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Aided Design ◽  
Level Parallelism

The increased demand for processor-level parallelism has many-folded the challenges for SoC designers to design, simulate and verify/validate today’s Multi-core System-On-Chip (SoC) due to the increased system complexity. There is also a need to reduce the design cycle time to produce a complex multi-core SOC system thereby the product can be brought into the market within an affordable time. The Computer-Aided Design (CAD) tools and Field Programmable Gate Arrays (FPGAs) provide a solution for rapidly prototyping and validating the system. This paper presents an implementation of multi-core SoC consisting of 6 Xilinx Micro-Blaze soft-core processors integrated to the Zynq Processing System (PS) using IP Integrator and these cores will be communicated through AXI bus. The functionality of the system is verified using Micro-Blaze system debugger. The hardware framework for the implemented system is implemented and verified on FPGA.  

scholarly journals Deploying a Smart Queuing System on Edge with Intel OpenVINO Toolkit

2021 ◽  
Author(s):  
Rishit Dagli ◽  
Süleyman Eken
Keyword(s):  
Neural Networks ◽  
Deep Learning ◽  
Public Transportation ◽  
Queuing System ◽  
Processing Unit ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
The Cost ◽  
Hardware Platforms

Abstract Recent increases in computational power and the development of specialized architecture led to the possibility to perform machine learning, especially inference, on the edge. OpenVINO is a toolkit based on Convolutional Neural Networks that facilitates fast-track development of computer vision algorithms and deep learning neural networks into vision applications, and enables their easy heterogeneous execution across hardware platforms. A smart queue management can be the key to the success of any sector.} In this paper, we focus on edge deployments to make the Smart Queuing System (SQS) accessible by all also providing ability to run it on cheap devices. This gives it the ability to run the queuing system deep learning algorithms on pre-existing computers which a retail store, public transportation facility or a factory may already possess thus considerably reducing the cost of deployment of such a system. SQS demonstrates how to create a video AI solution on the edge. We validate our results by testing it on multiple edge devices namely CPU, Integrated Edge Graphic Processing Unit (iGPU), Vision Processing Unit (VPU) and Field Programmable Gate Arrays (FPGAs). Experimental results show that deploying a SQS on edge is very promising.

scholarly journals Benchmarking Analysis of Space-Grade Central Processing Units and Field-Programmable Gate Arrays

2018 ◽  
Vol 15 (8) ◽  
pp. 518-529 ◽  
Author(s):  
Tyler M. Lovelly ◽  
Travis W. Wise ◽  
Shaun H. Holtzman ◽  
Alan D. George
Keyword(s):  
Field Programmable Gate Arrays ◽  
Central Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Ideal Compliant Joints and Integration of Computer Aided Design and Analysis

2015 ◽  
Vol 10 (2) ◽  
Author(s):  
Ashraf M. Hamed ◽  
Paramsothy Jayakumar ◽  
Michael D. Letherwood ◽  
David J. Gorsich ◽  
Antonio M. Recuero ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Processing Unit ◽  
B Spline ◽  
Constraint Equations ◽  
Central Processing ◽  
Compliant Joints ◽  
Linear Algebraic Equations ◽  
Dependent Variables ◽  
Computer Aided ◽  
Aided Design

This paper discusses fundamental issues related to the integration of computer aided design and analysis (I-CAD-A) by introducing a new class of ideal compliant joints that account for the distributed inertia and elasticity. The absolute nodal coordinate formulation (ANCF) degrees of freedom are used in order to capture modes of deformation that cannot be captured using existing formulations. The ideal compliant joints developed can be formulated, for the most part, using linear algebraic equations, allowing for the elimination of the dependent variables at a preprocessing stage, thereby significantly reducing the problem dimension and array storage needed. Furthermore, the constraint equations are automatically satisfied at the position, velocity, and acceleration levels. When using the proposed approach to model large scale chain systems, differences in computational efficiency between the augmented formulation and the recursive methods are eliminated, and the central processing unit (CPU) times resulting from the use of the two formulations become similar regardless of the complexity of the system. The elimination of the joint constraint equations and the associated dependent variables also contribute to the solution of a fundamental singularity problem encountered in the analysis of closed loop chains and mechanisms by eliminating the need to repeatedly change the chain or mechanism independent coordinates. It is shown that the concept of the knot multiplicity used in computational geometry methods, such as B-spline and NURBS (nonuniform rational B-spline), to control the degree of continuity at the breakpoints is not suited for the formulation of many ideal compliant joints. As explained in this paper, this issue is closely related to the inability of B-spline and NURBS to model structural discontinuities. Another contribution of this paper is demonstrating that large deformation ANCF finite elements can be effective, in some multibody systems (MBS) applications, in solving small deformation problems. This is demonstrated using a heavily constrained tracked vehicle with flexible-link chains. Without using the proposed approach, modeling such a complex system with flexible links can be very challenging. The analysis presented in this paper also demonstrates that adding significant model details does not necessarily imply increasing the complexity of the MBS algorithm.

Development of FPGA-Based Safety-Related I&C Systems

2004 ◽  
Author(s):  
Naotaka Oda ◽  
Teruji Tarumi ◽  
Atsushi Tanaka ◽  
Mikio Izumi ◽  
Toshifumi Sato
Keyword(s):  
Analog Circuits ◽  
Digital Circuit ◽  
The Other ◽  
Development Method ◽  
Central Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Long Life ◽  
Conventional Systems

Toshiba has developed FPGA-based systems which perform signal processing by field programmable gate arrays (FPGA) for safety-related I&C systems. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing units (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. Considering application to safety-related systems, nonvolatile and non rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. The systems which Toshiba developed this time are Power range Monitor (PRM) and Trip Module (TM). These systems are compatible with the conventional analog-based systems and the CPU-based systems. Therefore, requested cost for upgrading will be minimized. Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on.

Combining Multiple Optimized FPGA-based Pulsar Search Modules Using OpenCL

2019 ◽  
Vol 08 (03) ◽  
pp. 1950008 ◽  
Author(s):  
Haomiao Wang ◽  
Prabu Thiagaraj ◽  
Oliver Sinnen
Keyword(s):  
High Speed ◽  
Design Space ◽  
Hardware Accelerators ◽  
Gate Arrays ◽  
Fast Prototyping ◽  
Multiple Input ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Square Kilometer Array ◽  
High Level

Field-Programmable Gate Arrays (FPGAs) are widely used in the central signal processing design of the Square Kilometer Array (SKA) as hardware accelerators. The frequency domain acceleration search (FDAS) module is an important part of the SKA1-MID pulsar search engine. To develop for a yet to be finalized hardware, for cross-discipline interoperability and to achieve fast prototyping, OpenCL as a high-level FPGA synthesis approaches employed to create the sub-modules of FDAS. The FT convolution and the harmonic-summing plus some other minor sub-modules are elements in the FDAS module that have been well-optimized separately before. In this paper, we explore the design space of combining well-optimized designs, dealing with the ensuing need to trade-off and compromise. Pipeline computing is employed to handle multiple input arrays at high speed. The hardware target is to employ multiple high-end FPGAs to process the combined FDAS module. The results show interesting consequences, where the best individual solutions are not necessarily the best solutions for the speed of a pipeline where FPGA resources and memory bandwidth need to be shared. By proposing multiple buffering techniques to the pipeline, the combined FDAS module can achieve up to 2[Formula: see text] speedup over implementations without pipeline computing. We perform an extensive experimental evaluation on multiple high-end FPGA cards hosted in a workstation and compare to a technology comparable mid-range GPU.

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