scholarly journals Real-Time Monte Carlo Optimization on FPGA for the Efficient and Reliable Message Chain Structure

Electronics ◽  
2019 ◽  
Vol 8 (8) ◽  
pp. 866 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim
Keyword(s):  
Monte Carlo ◽  
Real Time ◽  
Communication Systems ◽  
Optimization Method ◽  
Chain Structure ◽  
Processing Unit ◽  
Monte Carlo Optimization ◽  
Central Processing ◽  
Field Programmable ◽  
Programmable Gate Arrays

This paper addresses the real-time optimization problem to find the most efficient and reliable message chain structure in data communications based on half-duplex command–response protocols such as MIL-STD-1553B communication systems. This paper proposes a real-time Monte Carlo optimization method implemented on field programmable gate arrays (FPGA) which can not only be conducted very quickly but also avoid the conflicts with other tasks on a central processing unit (CPU). Evaluation results showed that the proposed method can consistently find the optimal message chain structure within a quite small and deterministic time, which was much faster than the conventional Monte Carlo optimization method on a CPU.

scholarly journals Real-Time Particle Swarm Optimization on FPGA for the Optimal Message-Chain Structure

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 274 ◽  
Author(s):  
Heoncheol Lee ◽  
Kipyo Kim ◽  
Yongsung Kwon ◽  
Eonpyo Hong
Keyword(s):  
Particle Swarm Optimization ◽  
Real Time ◽  
Particle Swarm ◽  
Chain Structure ◽  
Processing Unit ◽  
Swarm Optimization ◽  
Central Processing ◽  
Time Optimization ◽  
New Variant ◽  
Real Time Optimization

This paper addresses the real-time optimization problem of the message-chain structure to maximize the throughput in data communications based on half-duplex command-response protocols. This paper proposes a new variant of the particle swarm optimization (PSO) algorithm to resolve real-time optimization, which is implemented on field programmable gate arrays (FPGA) to be performed faster in parallel and to avoid the delays caused by other tasks on a central processing unit. The proposed method was verified by finding the optimal message-chain structure much faster than the original PSO, as well as reliably with different system and algorithm parameters.

scholarly journals HARDWARE IMPLEMENTATION OF AN ENCRYPTION FOR ENHANCEMENT DGHV

2019 ◽  
Vol 2 (2) ◽  
pp. 44-57
Author(s):  
Zainab H. Mahmood ◽  
Mahmood K. Ibrahem
Keyword(s):  
Real Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Graphics Processing Unit ◽  
Homomorphic Encryption ◽  
Processing Unit ◽  
Fully Homomorphic Encryption ◽  
Encryption Schemes ◽  
Field Programmable ◽  
Programmable Gate Arrays

In constructing a secure and reliable cloud computing environment, a fully homomorphic encryption (FHE) scheme is conceived as a major cryptographic tool, as it enables arbitrary arithmetic evaluation of a cipher text without revealing the plaintext. However, due to very high of fully homomorphic encryption systems stays impractical and unfit for real-time applications  One way to address this restriction is by using graphics processing unit (GPUs) and field programmable gate arrays (FPGAs) to produce homomorphic encryption schemes. This paper represents the hardware implementation of an encryption for enhancement van Dijk, Gentry, Halevi and Vaikuntanathan’s (DGHV) scheme over the integer (DGHV10) using FPGA technology for high speed computation and real time results. The proposed method was simulated via Vivado system generator tools. Then design systems of fully homomrphic encryption are implemented in an FPGA hardware successfully using NEXYS 4 DDR board with ARTIX 7 XC7A100T FPGA. The Experimental results show that the FPGA- based fully homomorphic encryption system is 63 times faster than the simulation based implementation.

The Application of the Combination of Monte Carlo Optimization Method based QSAR Modeling and Molecular Docking in Drug Design and Development

2020 ◽  
Vol 20 (14) ◽  
pp. 1389-1402 ◽  
Author(s):  
Maja Zivkovic ◽  
Marko Zlatanovic ◽  
Nevena Zlatanovic ◽  
Mladjan Golubović ◽  
Aleksandar M. Veselinović
Keyword(s):  
Monte Carlo ◽  
Molecular Docking ◽  
Computer Calculation ◽  
Molecular Graph ◽  
Optimization Method ◽  
Docking Studies ◽  
Optimization Approach ◽  
Qsar Modeling ◽  
Monte Carlo Optimization ◽  
Molecular Docking Studies

In recent years, one of the promising approaches in the QSAR modeling Monte Carlo optimization approach as conformation independent method, has emerged. Monte Carlo optimization has proven to be a valuable tool in chemoinformatics, and this review presents its application in drug discovery and design. In this review, the basic principles and important features of these methods are discussed as well as the advantages of conformation independent optimal descriptors developed from the molecular graph and the Simplified Molecular Input Line Entry System (SMILES) notation compared to commonly used descriptors in QSAR modeling. This review presents the summary of obtained results from Monte Carlo optimization-based QSAR modeling with the further addition of molecular docking studies applied for various pharmacologically important endpoints. SMILES notation based optimal descriptors, defined as molecular fragments, identified as main contributors to the increase/ decrease of biological activity, which are used further to design compounds with targeted activity based on computer calculation, are presented. In this mini-review, research papers in which molecular docking was applied as an additional method to design molecules to validate their activity further, are summarized. These papers present a very good correlation among results obtained from Monte Carlo optimization modeling and molecular docking studies.

scholarly journals Embedded GPU Implementation for High-Performance Ultrasound Imaging

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 884
Author(s):  
Stefano Rossi ◽  
Enrico Boni
Keyword(s):  
High Performance ◽  
Graphics Processing Unit ◽  
Digital Signal ◽  
Processing Unit ◽  
Embedded Computing ◽  
Field Programmable ◽  
Peripheral Component Interconnect ◽  
Programmable Gate Arrays ◽  
Graphics Processing ◽  
Signal Processors

Methods of increasing complexity are currently being proposed for ultrasound (US) echographic signal processing. Graphics Processing Unit (GPU) resources allowing massive exploitation of parallel computing are ideal candidates for these tasks. Many high-performance US instruments, including open scanners like ULA-OP 256, have an architecture based only on Field-Programmable Gate Arrays (FPGAs) and/or Digital Signal Processors (DSPs). This paper proposes the implementation of the embedded NVIDIA Jetson Xavier AGX module on board ULA-OP 256. The system architecture was revised to allow the introduction of a new Peripheral Component Interconnect Express (PCIe) communication channel, while maintaining backward compatibility with all other embedded computing resources already on board. Moreover, the Input/Output (I/O) peripherals of the module make the ultrasound system independent, freeing the user from the need to use an external controlling PC.

scholarly journals Implementación de redes neuronales en FPGAs usando tipos de datos de punto fijo

2020 ◽  
Vol 8 ◽  
Author(s):  
Daniel Enériz Orta ◽  
Nicolás Medrano Marqués ◽  
Belén Calvo López
Keyword(s):  
Field Programmable Gate Array ◽  
A Priori ◽  
Central Processing Unit ◽  
Processing Unit ◽  
Central Processing ◽  
Field Programmable ◽  
Gate Array

La capacidad de estimar funciones no lineales hace que las redes neuronales sean una de las herramientas más usadas para aplicar fusión sensorial, permitiendo combinar la salida de diferentes sensores para obtener información de la que a priori no se dispone. Por otra parte, la capacidad de procesamiento paralelo de las FPGAs (Field-Programmable Gate Array) las hace idóneas para implementar redes neuronales ubicuas, permitiendo inferir resultados más rápido que una CPU (Central Processing Unit) sin necesidad de una conexión activa a internet. De esta forma, en este artículo se propone un flujo de trabajo para diseñar, entrenar e implementar una red neuronal en una FPGA Xilinx PYNQ Z2 que use tipos de dato de punto fijo para hacer fusión sensorial. Dicho flujo de trabajo es probado mediante el desarrollo de una red neuronal que combine las salidas de una nariz artificial de 16 sensores para obtener una estimación de las concentraciones de CH4 y C2H4.

An efficient solution for fast generation of multi-GNSS real-time products

2021 ◽  
Author(s):  
Hongjie Zheng ◽  
Hanyu Chang ◽  
Yongqiang Yuan ◽  
Qingyun Wang ◽  
Yuhao Li ◽  
...  
Keyword(s):  
Data Processing ◽  
Real Time ◽  
Processing Time ◽  
Efficient Solution ◽  
Gpu Computing ◽  
Sampling Rate ◽  
Precise Orbit Determination ◽  
Processing Unit ◽  
Processing Efficiency ◽  
Central Processing

<p>Global navigation satellite systems (GNSS) have been playing an indispensable role in providing positioning, navigation and timing (PNT) services to global users. Over the past few years, GNSS have been rapidly developed with abundant networks, modern constellations, and multi-frequency observations. To take full advantages of multi-constellation and multi-frequency GNSS, several new mathematic models have been developed such as multi-frequency ambiguity resolution (AR) and the uncombined data processing with raw observations. In addition, new GNSS products including the uncalibrated phase delay (UPD), the observable signal bias (OSB), and the integer recovery clock (IRC) have been generated and provided by analysis centers to support advanced GNSS applications.</p><p>       However, the increasing number of GNSS observations raises a great challenge to the fast generation of multi-constellation and multi-frequency products. In this study, we proposed an efficient solution to realize the fast updating of multi-GNSS real-time products by making full use of the advanced computing techniques. Firstly, instead of the traditional vector operations, the “level-3 operations” (matrix by matrix) of Basic Liner Algebra Subprograms (BLAS) is used as much as possible in the Least Square (LSQ) processing, which can improve the efficiency due to the central processing unit (CPU) optimization and faster memory data transmission. Furthermore, most steps of multi-GNSS data processing are transformed from serial mode to parallel mode to take advantage of the multi-core CPU architecture and graphics processing unit (GPU) computing resources. Moreover, we choose the OpenBLAS library for matrix computation as it has good performances in parallel environment.</p><p>       The proposed method is then validated on a 3.30 GHz AMD CPU with 6 cores. The result demonstrates that the proposed method can substantially improve the processing efficiency for multi-GNSS product generation. For the precise orbit determination (POD) solution with 150 ground stations and 128 satellites (GPS/BDS/Galileo/GLONASS/QZSS) in ionosphere-free (IF) mode, the processing time can be shortened from 50 to 10 minutes, which can guarantee the hourly updating of multi-GNSS ultra-rapid orbit products. The processing time of uncombined POD can also be reduced by about 80%. Meanwhile, the multi-GNSS real-time clock products can be easily generated in 5 seconds or even higher sampling rate. In addition, the processing efficiency of UPD and OSB products can also be increased by 4-6 times.</p>

New Optimal Solutions for Real-Time Reconfigurable Periodic Asynchronous Operating System Tasks with Minimizations of Response Time

2012 ◽  
Vol 1 (4) ◽  
pp. 88-131 ◽  
Author(s):  
Hamza Gharsellaoui ◽  
Mohamed Khalgui ◽  
Samir Ben Ahmed
Keyword(s):  
Response Time ◽  
Real Time ◽  
Scheduling Algorithm ◽  
Processing Unit ◽  
Software Faults ◽  
Worst Case ◽  
Agent Based ◽  
Central Processing ◽  
Technical Solutions ◽  
Task Systems

Scheduling tasks is an essential requirement in most real-time and embedded systems, but leads to unwanted central processing unit (CPU) overheads. The authors present a real-time schedulability algorithm for preemptable, asynchronous and periodic reconfigurable task systems with arbitrary relative deadlines, scheduled on a uniprocessor by an optimal scheduling algorithm based on the earliest deadline first (EDF) principles and on the dynamic reconfiguration. A reconfiguration scenario is assumed to be a dynamic automatic operation allowing addition, removal or update of operating system’s (OS) functional asynchronous tasks. When such a scenario is applied to save the system at the occurrence of hardware-software faults, or to improve its performance, some real-time properties can be violated. The authors propose an intelligent agent-based architecture where a software agent is used to satisfy the user requirements and to respect time constraints. The agent dynamically provides precious technical solutions for users when these constraints are not verified, by removing tasks according to predefined heuristic, or by modifying the worst case execution times (WCETs), periods, and deadlines of tasks in order to meet deadlines and to minimize their response time. They implement the agent to support these services which are applied to a Blackberry Bold 9700 and to a Volvo system and present and discuss the results of experiments.

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