2.1 dB noise figure 5.2 GHz CMOS low noise amplifier using wafer-level integrated passive device technology with a DC power consumption of 10 mW

2012 ◽  
Vol 6 (11) ◽  
pp. 1286-1290 ◽  
Author(s):  
K.-C. Lin ◽  
H.-K. Chiou ◽  
Y.-Z. Juang ◽  
D.-C. Chang
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Wafer Level ◽  
Passive Device ◽  
Dc Power ◽  
Noise Amplifier ◽  
Device Technology

DC Power-Optimized Ka-Band GaN-on-Si Low-Noise Amplifier With 1.5 dB Noise Figure

2022 ◽  
pp. 1-4
Author(s):  
L. Pace ◽  
P. E. Longhi ◽  
W. Ciccognani ◽  
S. Colangeli ◽  
F. Vitulli ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ka Band ◽  
Dc Power ◽  
Noise Amplifier ◽  
Gan On Si

Design of High Performance Low-Noise Amplifier Circuit Based on Complementary Metal Oxide Semiconductor Technology

2021 ◽  
Vol 16 (4) ◽  
pp. 559-564
Author(s):  
Chao Huang ◽  
Wan-Jun Yin
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Input Device ◽  
Output Stage ◽  
Noise Amplifier ◽  
5 Ghz

This paper designs a body-biased (BB) differential cascode low-noise amplifier (LNA) with current bias (CR) and capacitor cross-coupling (CCC) technology that meets the bandwidth requirements of 5 GHz wireless applications. In the design, the CCC technology in the differential cascode topology is used to effectively suppress the common mode noise, thereby improving the noise figure. The series resonant network eliminates parasitic capacitance at the input and output ends, thereby improving the power transmission efficiency. The CR technology formed by the intermediate capacitor shares the DC current input to the output device, thereby increasing the gain. This paper uses BB technology in the design to lower the threshold of the cascode device and improve the transconductance, which further improves the gain and reduces the power consumption. The CCC technology used in the paper improves linearity by eliminating the non-linear components present in the input device, which will not interfere with the transconductance of the output stage. This article has obtained excellent performance parameters including gain, noise figure (NF) and linearity without affecting the power consumption, integration and cost of the proposed design.

scholarly journals Adaptive low-power CMOS LNA in internet of things based wireless sensor networks

2020 ◽  
Vol 9 (3) ◽  
pp. 616
Author(s):  
Abdelhamid Helali ◽  
Feten Ouni ◽  
Mohsen Nasri ◽  
Hassen Maaref
Keyword(s):  
Internet Of Things ◽  
Power Consumption ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Rf Receiver ◽  
Noise Amplifier ◽  
Battery Energy

With the increasing need for the Internet of things (IoT), wireless communication has become a popular technology for the network. This explosion of IoT wireless applications makes the power consumption a key metric in the design of wireless sensor nodes. The major constraint of the wireless sensors nodes is battery energy, which is the mainly challenging problem in designing IoT network. these constraints have imposed new yet stringent specs to the design of RF front-ends. The design of adaptive radio-frequency circuits, in order to reduce power consumption, is of interest. In a RF receiver chain, the Low Noise Amplifier (LNA) stand as critical elements on the power consumption.To address this purpose, this paper proposes a design strategy for an adaptive Low Noise Amplifier as the first element of the receiver chain. Hence the proposed LNA achieves the correct QoS for various scenario of communications. Using the proposed LNA, a significant trade-off between a conversion gain, noise figure and energy consumption is presented.  

scholarly journals Design and Analysis of Cascode LNA for 60 GHz Wireless Applications

2019 ◽  
Vol 8 (9) ◽  
pp. 1399-1403
Keyword(s):  
Power Dissipation ◽  
Design Methodology ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
60 Ghz ◽  
Unconditionally Stable ◽  
Wireless Applications ◽  
Dc Power ◽  
Noise Amplifier

Design methodology and analysis of a 60GHz-band Low Noise Amplifier (LNA) is presented in this paper. The LNA has been designed and simulated using source degenerated cascode topology in 90 nm CMOS for operation at 60 GHz. The structured LNA is minimized for its area with 50%. The designed LNA is computed with ADS and is verified its functionality in terms of Noise Figure (NF), Gain, Linearity, Power dissipation and Stability. The designed LNA uses 12 mW of dc power from a 1.5 V supply with 16.3 dB gain and a NF of 3.5 dB at 60 GHz. The designed LNA is unconditionally stable and has IIP3 of -9 dBm with FoM of 15.

scholarly journals LNA Prototype at 54 MHz to 88 MHz Using Discrete Components

2020 ◽  
Vol 4 (1) ◽  
pp. 32
Author(s):  
Prapto Nugroho ◽  
Ivan Muhammad Ihsan Izetbegovic ◽  
Wahyu Dewanto
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Area Network ◽  
Third Order ◽  
Regional Area ◽  
Technical Specifications ◽  
Noise Amplifier ◽  
Intercept Point

This paper presents a design and prototyping of a Low-Noise Amplifier (LNA) for Wireless Regional Area Network (WRAN) operating in TV broadcast bands between 54 MHz – 88 MHz. The LNA design was then implemented by using discrete components. Components values was obtained by utilized DC analysis according to specifications which follows the Institute of Electrical and Electronics Engineering (IEEE) 802.22 standard on WRAN technical specifications. Simulation with 88 MHz produced S11 = -5.72 dB, S12 = -41.57 dB, S21 = 15.07 dB, S22 = -4.76 dB, Noise Figure (NF) = 3.9 dB, Input Third Order Intercept Point (IIP3) = 2.21 dBm, and power consumption of 45.39 mW. Experiments results on 88 MHz showed S11 = -6.13 dB and S21 = 0.74 dB.

scholarly journals The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology

2020 ◽  
Vol 2020 ◽  
pp. 1-12
Author(s):  
Hemad Heidari Jobaneh
Keyword(s):  
Power Consumption ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Design System ◽  
Cmos Process ◽  
Ultralow Power ◽  
Noise Amplifier ◽  
5 Ghz

The calculation and design of an ultralow-power Low Noise Amplifier (LNA) are proposed in this paper. The LNA operates from 5 GHz to 10 GHz, and forward body biasing technique is used to bring down power consumption of the circuit. The design revolves around precise calculations related to input impedance, output impedance, and the gain of the circuit. MATLAB and Advanced Design System (ADS) are utilized to design and simulate the LNA. In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. Noise Figure (NF), input matching (S11), gain (S21), IIP3, and power dissipation are 1.46 dB–2.27 dB, −11.25 dB, 13.82 dB, −8.5, and 963 μW, respectively.

Measurement of a 270 GHz Low Noise Amplifier With 7.5 dB Noise Figure

2007 ◽  
Vol 17 (7) ◽  
pp. 546-548 ◽  
Author(s):  
T. Gaier ◽  
L. Samoska ◽  
A. Fung ◽  
W. R. Deal ◽  
V. Radisic ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Noise Amplifier

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

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