Robust design of low power CMOS analogue integrated circuits

2001 ◽  
Vol 148 (4) ◽  
pp. 197 ◽  
Author(s):  
T.B. Tarim ◽  
M. Ismail
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Robust Design ◽  
Low Power Cmos ◽  
Analogue Integrated Circuits ◽  
Cmos Analogue Integrated Circuits

Low-power CMOS integrated circuits for radio frequency applications

2005 ◽  
Vol 152 (5) ◽  
pp. 509 ◽  
Author(s):  
M.J. Deen ◽  
R. Murji ◽  
A. Fakhr ◽  
N. Jafferali ◽  
W.L. Ngan
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Radio Frequency ◽  
Cmos Integrated Circuits ◽  
Low Power Cmos

A design for testability approach for nano-CMOS analogue integrated circuits

2013 ◽  
Vol 100 (6) ◽  
pp. 837-850 ◽  
Author(s):  
Mouna Karmani ◽  
Chiraz Khedhiri ◽  
Belgacem Hamdi ◽  
Ka Lok Man ◽  
Rached Tourki
Keyword(s):  
Integrated Circuits ◽  
Design For Testability ◽  
Analogue Integrated Circuits ◽  
Cmos Analogue Integrated Circuits

GaAs sampled-analogue integrated circuits

1987 ◽  
Vol 57 (1S) ◽  
pp. S35
Author(s):  
J.A. Phillips ◽  
S.J. Harrold ◽  
G.K. Barker
Keyword(s):  
Integrated Circuits ◽  
Analogue Integrated Circuits

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

PVT ‐compensated low‐voltage and low‐power CMOS LNA for IoT applications

2020 ◽  
Vol 30 (11) ◽  
Author(s):  
Sajad Nejadhasan ◽  
Fatemeh Zaheri ◽  
Ebrahim Abiri ◽  
Mohammad Reza Salehi
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Iot Applications ◽  
Low Power Cmos ◽  
Cmos Lna
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