scholarly journals GPU Usage in ATLAS Reconstruction and Analysis

2020 ◽  
Vol 245 ◽  
pp. 05006
Author(s):  
Attila Krasznahorkay ◽  
Charles Leggett ◽  
Alaettin Serhan Mete ◽  
Scott Snyder ◽  
Vakho Tsulaia
Keyword(s):  
Data Model ◽  
Memory Management ◽  
High Performance ◽  
Event Data ◽  
Software Environment ◽  
The Past ◽  
Graphical Processing Units ◽  
Different Types ◽  
Graphical Processing ◽  
Performance Computing

With Graphical Processing Units (GPUs) and other kinds of accelerators becoming ever more accessible, High Performance Computing Centres all around the world using them ever more, ATLAS has to find the best way of making use of such accelerators in much of its computing. Tests with GPUs – mainly with CUDA – have been performed in the past in the experiment. At that time the conclusion was that it was not advantageous for the ATLAS offline and trigger software to invest time and money into GPUs. However as the usage of accelerators has become cheaper and simpler in recent years, their re-evaluation in ATLAS’s offline software is warranted. We show new results of using GPU accelerated calculations in ATLAS’s offline software environment using the ATLAS offline/analysis (xAOD) Event Data Model. We compare the performance and flexibility of a couple of the available GPU programming methods, and show how different memory management setups affect our ability to offload different types of calculations to a GPU efficiently.

High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects

2014 ◽  
pp. 513-532
Author(s):  
Rasit O. Topaloglu ◽  
Swati R. Manjari ◽  
Saroj K. Nayak
Keyword(s):  
Integrated Circuits ◽  
High Performance Computing ◽  
Real World ◽  
High Performance ◽  
Quantum Effects ◽  
Accurate Analysis ◽  
Graphical Processing Units ◽  
Graphical Processing ◽  
Silicon Based ◽  
Performance Computing

Interconnects in semiconductor integrated circuits have shrunk to nanoscale sizes. This size reduction requires accurate analysis of the quantum effects. Furthermore, improved low-resistance interconnects need to be discovered that can integrate with biological and nanoelectronic systems. Accurate system-scale simulation of these quantum effects is possible with high-performance computing (HPC), while high cost and poor feasibility of experiments also suggest the application of simulation and HPC. This chapter introduces computational nanoelectronics, presenting real-world applications for the simulation and analysis of nanoscale and molecular interconnects, which may provide the connection between molecules and silicon-based devices. We survey computational nanoelectronics of interconnects and analyze four real-world case studies: 1) using graphical processing units (GPUs) for nanoelectronic simulations; 2) HPC simulations of current flow in nanotubes; 3) resistance analysis of molecular interconnects; and 4) electron transport improvement in graphene interconnects. In conclusion, HPC simulations are promising vehicles to advance interconnects and study their interactions with molecular/biological structures in support of traditional experimentation.

High-Performance Computing for Theoretical Study of Nanoscale and Molecular Interconnects

2012 ◽  
pp. 78-97
Author(s):  
Rasit O. Topaloglu ◽  
Swati R. Manjari ◽  
Saroj K. Nayak
Keyword(s):  
Integrated Circuits ◽  
High Performance Computing ◽  
Real World ◽  
High Performance ◽  
Quantum Effects ◽  
Accurate Analysis ◽  
Graphical Processing Units ◽  
Graphical Processing ◽  
Silicon Based ◽  
Performance Computing

Interconnects in semiconductor integrated circuits have shrunk to nanoscale sizes. This size reduction requires accurate analysis of the quantum effects. Furthermore, improved low-resistance interconnects need to be discovered that can integrate with biological and nanoelectronic systems. Accurate system-scale simulation of these quantum effects is possible with high-performance computing (HPC), while high cost and poor feasibility of experiments also suggest the application of simulation and HPC. This chapter introduces computational nanoelectronics, presenting real-world applications for the simulation and analysis of nanoscale and molecular interconnects, which may provide the connection between molecules and silicon-based devices. We survey computational nanoelectronics of interconnects and analyze four real-world case studies: 1) using graphical processing units (GPUs) for nanoelectronic simulations; 2) HPC simulations of current flow in nanotubes; 3) resistance analysis of molecular interconnects; and 4) electron transport improvement in graphene interconnects. In conclusion, HPC simulations are promising vehicles to advance interconnects and study their interactions with molecular/biological structures in support of traditional experimentation.

Using GPUs to compute fast Fourier transforms for crystal structure solution and refinement

2013 ◽  
Vol 46 (3) ◽  
pp. 594-600 ◽  
Author(s):  
ElSayed Mohamed Shalaby ◽  
Miguel Afonso Oliveira
Keyword(s):  
Crystal Structure ◽  
Fourier Transformation ◽  
Fourier Transforms ◽  
Fast Fourier Transformation ◽  
Parallel Calculations ◽  
The Past ◽  
Graphical Processing Units ◽  
Software Algorithms ◽  
Structure Solution ◽  
Graphical Processing

In the past few years, new hardware tools have become available for computing using the graphical processing units (GPUs) present in modern graphics cards. These GPUs allow efficient parallel calculations with a much higher throughput than microprocessors. In this work, fast Fourier transformation calculations used inSIR2011software algorithms have been carried out using the power of the GPU, and the speed of the calculations has been compared with that achieved using normal CPUs.

Efficient Graph Component Labeling on Hybrid CPU and GPU Platforms

2014 ◽  
Vol 596 ◽  
pp. 276-279
Author(s):  
Xiao Hui Pan
Keyword(s):  
High Performance ◽  
General Purpose ◽  
Gpu Programming ◽  
Data Parallel ◽  
Graphical Processing Units ◽  
Architectural Features ◽  
Graph Coloring Problem ◽  
Graphical Processing ◽  
And Performance ◽  
Performance Results

Graph component labeling, which is a subset of the general graph coloring problem, is a computationally expensive operation in many important applications and simulations. A number of data-parallel algorithmic variations to the component labeling problem are possible and we explore their use with general purpose graphical processing units (GPGPUs) and with the CUDA GPU programming language. We discuss implementation issues and performance results on CPUs and GPUs using CUDA. We evaluated our system with real-world graphs. We show how to consider different architectural features of the GPU and the host CPUs and achieve high performance.

scholarly journals High-performance computing environment: a review of twenty years of experiments in China

2016 ◽  
Vol 3 (1) ◽  
pp. 36-48 ◽  
Author(s):  
Zhiwei Xu ◽  
Xuebin Chi ◽  
Nong Xiao
Keyword(s):  
High Performance Computing ◽  
High Performance ◽  
The Internet ◽  
Computing Environment ◽  
Open Problems ◽  
Loosely Coupled ◽  
The Past ◽  
Important Open Problem ◽  
Computing Environments ◽  
Performance Computing

Abstract A high-performance computing environment, also known as a supercomputing environment, e-Science environment or cyberinfrastructure, is a crucial system that connects users’ applications to supercomputers, and provides usability, efficiency, sharing, and collaboration capabilities. This review presents important lessons drawn from China's nationwide efforts to build and use a high-performance computing environment over the past 20 years (1995–2015), including three observations and two open problems. We present evidence that such an environment helps to grow China's nationwide supercomputing ecosystem by orders of magnitude, where a loosely coupled architecture accommodates diversity. An important open problem is why technology for global networked supercomputing has not yet become as widespread as the Internet or Web. In the next 20 years, high-performance computing environments will need to provide zettaflops computing capability and 10 000 times better energy efficiency, and support seamless human-cyber-physical ternary computing.

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