High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.
W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology