A W-Band transmitter channel with 16dBm output power and a receiver channel with 58.6mW DC power consumption using heterogeneously integrated InP HBT and Si CMOS technologies

2019 ◽  
Author(s):  
Ahmed S. H. Ahmed ◽  
Arda Simsek ◽  
Ali A. Farid ◽  
Andrew D. Carter ◽  
Miguel Urteaga ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Dc Power ◽  
W Band

scholarly journals W-band voltage-controlled oscillator design in 130 nm SiGe BiCMOS technology

2019 ◽  
Vol 30 ◽  
pp. 01006
Author(s):  
Alexander Kozhemyakin ◽  
Ivan Kravchenko
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Design Flow ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
W Band ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
Fundamental Oscillation ◽  
Simulation Results

The paper presents design flow and simulation results of the W-band fundamental voltage-controlled oscillator in 0.13 μm SiGe BiCMOS technology for an automotive radar application. Oscillator provides fundamental oscillation range of 76.8 GHz to 81.2 GHz. According to simulation results phase noise is –89.3 dBc/Hz at 1 MHz offset, output power is –5.6 dBm and power consumption is 39 mW from 3.3 V source.

scholarly journals A 270-GHz Push-Push Transformer-Based Oscillator Adopting Power Leakage Suppression Technique

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1347
Author(s):  
Dzuhri Radityo Utomo ◽  
Dae-Woong Park ◽  
Jong-Phil Hong ◽  
Sang-Gug Lee
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Loss ◽  
Dc Power ◽  
Leakage Path ◽  
Suppression Technique ◽  
Power Leakage

A push–push transformer-based oscillator (TBO) adopting a power leakage suppression technique has been proposed. The proposed technique reduces the power loss due to unwanted leakage path without additional DC power consumption, hence improving the output power and DC-to-RF efficiency. The measured output power of the proposed single core oscillator is −4.5 dBm at 270 GHz with 2.1% DC-to-RF efficiency.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

scholarly journals DC Power Consumption [Enigmas, etc.]

2021 ◽  
Vol 22 (7) ◽  
pp. 90-92
Author(s):  
Takashi Ohira
Keyword(s):  
Power Consumption ◽  
Dc Power

W-band GaN MMIC with 842 mW output power at 88 GHz

2010 ◽  
Author(s):  
M. Micovic ◽  
A. Kurdoghlian ◽  
K. Shinohara ◽  
I. Milosavljevic ◽  
S. D. Burnham ◽  
...  
Keyword(s):  
Output Power ◽  
W Band

scholarly journals Design of W-Band GaN-on-Silicon Power Amplifier Using Low Impedance Lines

2021 ◽  
Vol 11 (19) ◽  
pp. 9017
Author(s):  
Jinho Jeong ◽  
Yeongmin Jang ◽  
Jongyoun Kim ◽  
Sosu Kim ◽  
Wansik Kim
Keyword(s):  
Power Density ◽  
Output Power ◽  
Power Amplifier ◽  
High Power ◽  
Common Source ◽  
High Electron ◽  
Large Signal ◽  
Power Added Efficiency ◽  
W Band ◽  
Gan On Si

In this paper, a high-power amplifier integrated circuit (IC) in gallium-nitride (GaN) on silicon (Si) technology is presented at a W-band (75–110 GHz). In order to mitigate the losses caused by relatively high loss tangent of Si substrate compared to silicon carbide (SiC), low-impedance microstrip lines (20–30 Ω) are adopted in the impedance matching networks. They allow for the impedance transformation between 50 Ω and very low impedances of the wide-gate transistors used for high power generation. Each stage is matched to produce enough power to drive the next stage. A Lange coupler is employed to combine two three-stage common source amplifiers, providing high output power and good input/output return loss. The designed power amplifier IC was fabricated in the commercially available 60 nm GaN-on-Si high electron mobility transistor (HEMT) foundry. From on-wafer probe measurements, it exhibits the output power higher than 26.5 dBm and power added efficiency (PAE) higher than 8.5% from 88 to 93 GHz with a large-signal gain > 10.5 dB. Peak output power is measured to be 28.9 dBm with a PAE of 13.3% and a gain of 9.9 dB at 90 GHz, which corresponds to the power density of 1.94 W/mm. To the best of the authors’ knowledge, this result belongs to the highest output power and power density among the reported power amplifier ICs in GaN-on-Si HEMT technologies operating at the W-band.

Power Consumption Characteristics of Appliances in a Smart House powered by Multi-Phase Transformer-based DC Power

2021 ◽  
Author(s):  
Kazuki Ikeda ◽  
Masaki Tsunekawa ◽  
Yuto Iwasaki ◽  
Kazuto Yukita ◽  
Toshiro Matsumura ◽  
...  
Keyword(s):  
Power Consumption ◽  
Dc Power ◽  
Smart House ◽  
Multi Phase

A fully matched dual stage CMOS power amplifier with integrated passive linearizer attaining 23 db gain, 40% PAE and 28 DBM OIP3

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Premmilaah Gunasegaran ◽  
Jagadheswaran Rajendran ◽  
Selvakumar Mariappan ◽  
Yusman Mohd Yusof ◽  
Zulfiqar Ali Abdul Aziz ◽  
...  
Keyword(s):  
Power Consumption ◽  
Output Power ◽  
Power Amplifier ◽  
Maximum Output Power ◽  
Maximum Output ◽  
Power Gain ◽  
Matching Network ◽  
Content Type ◽  
Power Added Efficiency ◽  
Main Amplifier

Purpose The purpose of this paper is to introduce a new linearization technique known as the passive linearizer technique which does not affect the power added efficiency (PAE) while maintaining a power gain of more than 20 dB for complementary metal oxide semiconductor (CMOS) power amplifier (PA). Design/methodology/approach The linearization mechanism is executed with an aid of a passive linearizer implemented at the gate of the main amplifier to minimize the effect of Cgs capacitance through the generation of opposite phase response at the main amplifier. The inductor-less output matching network presents an almost lossless output matching network which contributes to high gain, PAE and output power. The linearity performance is improved without the penalty of power consumption, power gain and stability. Findings With this topology, the PA delivers more than 20 dB gain for the Bluetooth Low Energy (BLE) Band from 2.4 GHz to 2.5 GHz with a supply headroom of 1.8 V. At the center frequency of 2.45 GHz, the PA exhibits a gain of 23.3 dB with corresponding peak PAE of 40.11% at a maximum output power of 14.3 dBm. At a maximum linear output power of 12.7 dBm, a PAE of 37.3% has been achieved with a peak third order intermodulation product of 28.04 dBm with a power consumption of 50.58 mW. This corresponds to ACLR of – 20 dBc, thus qualifying the PA to operate for BLE operation. Practical implications The proposed technique is able to boost up the efficiency and output power, as well as linearize the PA closer to 1 dB compression point. This reduces the trade-off between linear output power and PAE in CMOS PA design. Originality/value The proposed CMOS PA can be integrated comfortably to a BLE transmitter, allowing it to reduce the transceiver’s overall power consumption.

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