Heterodyne lock-in thermal coupling measurements in integrated circuits: Applications to test and characterization

Abstract Lock-in thermography based on an infrared camera has proven to be a useful tool for failure analysis of integrated circuits (ICs). This article discusses four novel technical developments of lock-in thermography. These developments are blackening the IC surface with colloidal bismuth, the synchronous undersampling technique allowing the use of higher lock-in frequencies, displaying the 0deg/-90deg signal as a novel high resolution emissivity corrected image type, and removing the thermal blurring effect by mathematically deconvoluting the 0deg/-90deg; signal. The effect of these techniques is demonstrated by using a regularly working operational amplifier (pA 741) and a damaged capacitor as test devices. It is shown that blackening the IC surface improves the detection sensitivity in metallized regions by up to a factor of 10, whereas the other methods allow improvement of the effective spatial resolution. The article also discusses which of the spatial resolution improvement techniques is most appropriate in different situations.

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Correlation of Thermal Rise Time to Sample Depth in Multi-Die Stacked Devices

10.31399/asm.cp.istfa2018p0022 ◽

2018 ◽

Author(s):

M. Shi ◽

A.G. Street ◽

Y.F. Dai

Keyword(s):

Integrated Circuits ◽

Rise Time ◽

Thermal Source ◽

Memory Devices ◽

Digital Modulation ◽

Sample Depth ◽

Lock In ◽

Thermal Sources ◽

Stacked Memory

Abstract Dynamic Digital Modulation, an adaptation of Lock-In Thermography, has been shown to be a useful technique to establish the relative Z-depth of thermal sources in integrated circuits. In order to determine the specific depth of a thermal source it is necessary to correlate known depths to measured thermal rise time. In this work, multi-die stacked memory devices are used as calibration sources to correlate a thermal source at individual die to the measured thermal rise time.

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Thermal Failure Analysis of Functional Failures by IR Lock-in Thermal Emission

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0164 ◽

2019 ◽

Author(s):

Paul Hubert P. Llamera ◽

Camille Joyce G. Garcia-Awitan

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Near Infrared ◽

Thermal Emission ◽

Fault Localization ◽

Fault Isolation ◽

Distinct Advantage ◽

Infra Red ◽

Emission Microscopy ◽

Lock In

Abstract Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

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