Effect of channel widths on negative shift of threshold voltage, including stress-induced hump phenomenon in InGaZnO thin-film transistors under high-gate and drain bias stress

2012 ◽  
Vol 100 (4) ◽  
pp. 043503 ◽  
Author(s):  
Sung-Hwan Choi ◽  
Min-Koo Han
2015 ◽  
Vol 36 (6) ◽  
pp. 579-581 ◽  
Author(s):  
Jong In Kim ◽  
In-Tak Cho ◽  
Chan-Yong Jeong ◽  
Daeun Lee ◽  
Hyuck-In Kwon ◽  
...  

2006 ◽  
Vol 910 ◽  
Author(s):  
Kwang-Sub Shin ◽  
Jae-Hoon Lee ◽  
Won-kyu Lee ◽  
Sang-Geun Park ◽  
Min-Koo Han

AbstractThe threshold voltage (VT) degradation of asymmetric source-drain a-Si:H TFTs due to the electrical stress has been investigated. In the absence of a drain bias (VG=15V, VD=0V), the threshold voltage (VT) shifts of asymmetric TFTs were similar to that of symmetric TFT. However, in the presence of drain bias (VG=15V, VD=20V), the VT shifts of asymmetric TFTs were less than symmetric TFT. The VT shifts of ‘L’ and ‘J’ shaped TFT were 0.29V, 0.24V respectively, while the VT shift of ‘I’ shaped TFT was 0.42V.The less VT degradation of the asymmetric source-drain a-Si:H TFT compared with the symmetric TFT may be explained by the defect creation model. Since the actual drain width of asymmetric TFT is longer than symmetric TFT at the same W/L ratio, the charge depletion due to the drain bias is larger than that of the asymmetric TFT. Due to the less carrier concentration in the channel, the asymmetric a-Si:H TFT shows the less VT degradation compared with the symmetric TFT.


2012 ◽  
Vol 4 (10) ◽  
pp. 5369-5374 ◽  
Author(s):  
Jun Yong Bak ◽  
Sinhyuk Yang ◽  
Min Ki Ryu ◽  
Sang Hee Ko Park ◽  
Chi Sun Hwang ◽  
...  

1990 ◽  
Vol 192 ◽  
Author(s):  
Tetsu Ogawa ◽  
Sadayoshi Hotta ◽  
Horoyoshi Takezawa

ABSTRACTThrough the time and temperature dependence measurements on threshold voltage shifts (Δ VT) in amorphous silicon thin film transistors, it has been found that two separate instability mechanisms exist; within short stress time ranges Δ Vτ increases as log t and this behavior corresponds to charge trapping in SiN. On the other hand, in long stress time ranges Δ VT increases as t t/4 and can be explained by time-dependent creation of trap in a-Si.


Materials ◽  
2019 ◽  
Vol 12 (14) ◽  
pp. 2300
Author(s):  
He Zhang ◽  
Yaogong Wang ◽  
Ruozheng Wang ◽  
Xiaoning Zhang ◽  
Chunliang Liu

To improve the performance of amorphous InGaZnOx (a-IGZO) thin film transistors (TFTs), in this thesis, Cs+ ions adsorbed IGZO (Cs-IGZO) films were prepared through a solution immersion method at low temperature. Under the modification of surface structure and oxygen vacancies concentrations of a-IGZO film, with the effective introduction of Cs+ ions into the surface of a-IGZO films, the transfer properties and stability of a-IGZO TFTs are greatly improved. Different parameters of Cs+ ion concentrations were investigated in our work. When the Cs+ ions concentration reached 2% mol/L, the optimized performance Cs-IGZO TFT was obtained, showing the carrier mobility of 18.7 cm2 V−1 s−1, the OFF current of 0.8 × 10−10 A, and the threshold voltage of 0.2 V, accompanied by the threshold voltage shifts of 1.3 V under positive bias stress for 5000 s.


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