Heat removal in packaged high-power light-emitting diode (LED) chips is critical to device performance and reliability. Thermal performance of LEDs is important in that lowered junction temperatures extend the LED's lifetime at a given photometric flux (brightness). Optionally, lower thermal resistance can enable increased brightness operation without exceeding the maximum allowable Tj for a given lifetime. A significant portion of the junction-to-case thermal resistance comes from the joint between chip and substrate, or the die-attach layer. In this study, we evaluated three different types of leading die-attach materials; silver epoxy, lead-free solder, and an emerging nanosilver paste. Each of the three was processed via their respective physical and chemical mechanisms: epoxy curing by cross-linking of polymer molecules; intermetalic soldering by reflow and solidification; and nanosilver sintering by solid-state atomic diffusion. High-power LED chips with a chip area of 3.9 mm2 were attached by the three types of materials onto metalized aluminum nitride substrates, wire-bonded, and then tested in an electro-optical setup. The junction-to-heatsink thermal resistance of each LED assembly was determined by the wavelength shift methodology, described in detail in this paper. We found that the average thermal resistance in the chips attached by the nanosilver paste was the lowest, and it is the highest from the chips attached by the silver epoxy: the difference between the two was about 0.7°C/W, while the difference between the sintered and soldered was about 0.3°C/W. The lower thermal resistance in the sintered joints is expected to significantly improve the photometric flux from the device. Simple calculations, excluding high current efficiency droop, predict that the brightness improvement could be as high as 50% for the 3.9 mm2 chip. The samples will be functionally tested at high current, in both steady-state and pulsed operation, to determine brightness improvements, including the impact of droop. Nanosilver die-attach on a range of chip sizes up to 12 mm2 are also considered and discussed.
High-Porosity Thermal Barrier Coatings from High-Power Plasma Spray Equipment—Processing, Performance and Economics
