Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

2008 ◽  
Vol 95 (2) ◽  
pp. 139-157 ◽  
Author(s):  
Subhendu Kumar Sahoo ◽  
Chandra Shekhar
Keyword(s):  
High Speed ◽  
Partial Product ◽  
Parallel Multiplier ◽  
Dsp Applications

scholarly journals DA Based Systematic Approach Using Speculative Addition for High Speed DSP Applications

2018 ◽  
Vol 7 (2.24) ◽  
pp. 197
Author(s):  
G Reddy Hemantha ◽  
S Varadarajan ◽  
M N. Giriprasad
Keyword(s):  
Error Detection ◽  
High Speed ◽  
Systematic Approach ◽  
Processing Unit ◽  
Partial Product ◽  
Post Processing ◽  
Latency Reduction ◽  
Parallel Prefix ◽  
Variable Latency ◽  
Dsp Applications

In recent years Parallel-prefix topologies has been emerged to offer a high-speed solution for many DSP applications. Here in this paper carrier approximation is introduced to incorporate speculation in Han Carlson prefix method.  And overall latency is considerably reduced using single Brent-Kung addition as a pre and post processing unit. In order to improve the reliability error detection network is combined with the approximated adder and it is assert the error correction unit whenever speculation fails during carries propagation from LSB segment to MSB unit. The proposed speculative adder based on Han-Carlson parallel-prefix topology attains better latency reduction than variable latency Kogge-Stone topology. Finally, multiplier-accumulation unit (MAC) is designed using serial shift-based accumulation where the proposed speculative adder is used for partial product addition iteratively. The performance merits and latency reduction of proposed adder unit is proved through FPGA hardware synthesis. Obtained results show that proposed MAC unit outperforms both previously proposed speculative architectures and all other high-speed multiplication methods.  

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

2013 ◽  
Vol 2 (1) ◽  
pp. 15
Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil
Keyword(s):  
Binary Tree ◽  
High Speed ◽  
Hardware Implementation ◽  
Critical Path ◽  
Partial Product ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
Multiplication Process ◽  
Major Bottleneck ◽  
Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

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