On the local power dissipation of h.f. waves in hot inhomogeneous plasmas

1988 ◽  
Vol 30 (8) ◽  
pp. 1083-1092 ◽  
Author(s):  
M Brambilla ◽  
T Krucken
Keyword(s):  
Power Dissipation ◽  
Local Power

Influence of Overgrown Micropipes in the Active Area of SiC Schottky Diodes on Long Term Reliability

2005 ◽  
Vol 483-485 ◽  
pp. 925-928 ◽  
Author(s):  
Roland Rupp ◽  
Michael Treu ◽  
Peter Türkes ◽  
H. Beermann ◽  
Thomas Scherg ◽  
...  
Keyword(s):  
Leakage Current ◽  
Power Dissipation ◽  
Schottky Diodes ◽  
Physical Structure ◽  
Active Area ◽  
Clear Correlation ◽  
Local Power ◽  
Degradation Mechanisms ◽  
Failure Simulation

Other than open micropipes (MP), overgrown micropipes do not necessarily lead to a^significantly reduced blocking capability of the affected SiC device. However they can lead to a degradation of the device during operation. In this paper the physical structure of overgrown micropipes will be revealed and their contribution to the leakage current will be shown. The possible impact of the high local power dissipation in the surrounding of the overgrown micropipe will be discussed and long term degradation mechanisms will be described. Failure simulation under laboratory conditions shows a clear correlation between the position of overgrown micropipes and the location of destructive burnt spots.

scholarly journals Study of Local Power Dissipation in Ultrascaled Silicon Nanowire FETs

2015 ◽  
Vol 36 (1) ◽  
pp. 2-4 ◽  
Author(s):  
Antonio Martinez ◽  
John R. Barker ◽  
Manuel Aldegunde ◽  
Raul Valin
Keyword(s):  
Power Dissipation ◽  
Silicon Nanowire ◽  
Local Power

Analyzing the On-State Power Dissipation in Stepped-Output Diode-Clamped Multi-Level Inverter

2010 ◽  
Vol E93-C (12) ◽  
pp. 1670-1678 ◽  
Author(s):  
Ehsan ESFANDIARI ◽  
Norman Bin MARIUN ◽  
Mohammad Hamiruce MARHABAN ◽  
Azmi ZAKARIA
Keyword(s):  
Power Dissipation ◽  
State Power ◽  
Multi Level

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ring Counter ◽  
Low Power Dissipation

Enforcing Local Power Conservation for Metasurface Design Using Electromagnetic Inversion

2020 ◽  
Author(s):  
Trevor Brown ◽  
Yousef Vahabzadeh ◽  
Christophe Caloz ◽  
Puyan Mojabi
Keyword(s):  
Optimization Procedure ◽  
Incident Field ◽  
Additional Constraint ◽  
Two Dimensional ◽  
Local Power ◽  
Power Conservation ◽  
Cost Functional ◽  
Field Transformation

<pre>A method based on electromagnetic inversion is extended to facilitate the design of passive, lossless, and reciprocal metasurfaces. More specifically, the inversion step is modified to ensure that the field transformation satisfies local power conservation, using available knowledge of the incident field. This paper formulates a novel cost functional to apply this additional constraint, and describes the optimization procedure used to find a solution that satisfies both the user-defined field specifications and local power conservation. Lastly, the method is demonstrated with a two-dimensional (2D) example.</pre>

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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