Ga-doped indium oxide nanowire phase change random access memory cells

2014 ◽  
Vol 25 (5) ◽  
pp. 055205 ◽  
Author(s):  
Bo Jin ◽  
Taekyung Lim ◽  
Sanghyun Ju ◽  
Marat I Latypov ◽  
Hyoung Seop Kim ◽  
...  
2010 ◽  
Vol 49 (4) ◽  
pp. 04DD16 ◽  
Author(s):  
Hock Lee ◽  
textscShi Luping ◽  
textscZhao Rong ◽  
textscYang Hongxin ◽  
textscLim Kian Guan ◽  
...  

2014 ◽  
Vol 104 (10) ◽  
pp. 103510 ◽  
Author(s):  
Bo Jin ◽  
Taekyung Lim ◽  
Sanghyun Ju ◽  
Marat I. Latypov ◽  
Dong-Hai Pi ◽  
...  

Nanoscale ◽  
2021 ◽  
Vol 13 (8) ◽  
pp. 4678-4684
Author(s):  
Yan Cheng ◽  
Yonghui Zheng ◽  
Zhitang Song

A 3D nano-bicontinuous structure consisting of a reversible Sb2Te3 phase and amorphous Si phase is visualized. The amorphous Si frame is stable and the Sb2Te3 nano areas switch between the a- and f-structure.


2010 ◽  
Vol 13 (2) ◽  
pp. K8 ◽  
Author(s):  
Dongbok Lee ◽  
Sung-Soo Yim ◽  
Ho-Ki Lyeo ◽  
Min-Ho Kwon ◽  
Dongmin Kang ◽  
...  

2006 ◽  
Vol 45 (5A) ◽  
pp. 3955-3958 ◽  
Author(s):  
X. S. Miao ◽  
L. P. Shi ◽  
H. K. Lee ◽  
J. M. Li ◽  
R. Zhao ◽  
...  

2005 ◽  
Vol 98 (1) ◽  
pp. 013520 ◽  
Author(s):  
V. Giraud ◽  
J. Cluzel ◽  
V. Sousa ◽  
A. Jacquot ◽  
A. Dauscher ◽  
...  

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.


2008 ◽  
Vol 1072 ◽  
Author(s):  
Jianming Li ◽  
L.P. Shi ◽  
H.X. Yang ◽  
K.G. Lim ◽  
X.S. Miao ◽  
...  

ABSTRACTThree-dimensional finite element method (FEM) is used to solve the thermal strain-stress fields of phase-change random access memory (PCRAM) cells. Simulation results show that thermal stress concentrates at the interfaces between electrodes and phase change layer and it is significantly larger than that within the phase change layer. It has been found that the peak thermal stress is linearly related to the voltage of electrical pulse in the reset process but once amorphous state is produced in the cell, a nonlinear relationship between thermal stress and electrical power exists. This paper reported the change of thermal stress during set process. It was found that the stress decreases significantly due to the amorphous active region during set processes.


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