A versatile low-resistance ohmic contact process with ohmic recess and low-temperature annealing for GaN HEMTs

2018 ◽  
Vol 33 (9) ◽  
pp. 095019 ◽  
Author(s):  
Yen-Ku Lin ◽  
Johan Bergsten ◽  
Hector Leong ◽  
Anna Malmros ◽  
Jr-Tai Chen ◽  
...  
2000 ◽  
Vol 338-342 ◽  
pp. 1619-1619
Author(s):  
L.S. Tan ◽  
A. Raman ◽  
K.M. Ng ◽  
S.J. Chua ◽  
A.T.S. Wee ◽  
...  

“removed due to double publication”. The original paper: Journal: Semiconductor Science and Technology Create an alertIssue Volume 15, Number 6 Citation: L S Tan et al 2000 Semicond. Sci. Technol. 15 585 doi: 10.1088/0268-1242/15/6/317 can be accesses at IOP: http://iopscience.iop.org/0268-1242/15/6/317


2012 ◽  
Vol 538-541 ◽  
pp. 2207-2210
Author(s):  
Sung Jin Cho ◽  
Cong Wang ◽  
Nam Young Kim

In the process of characterizing AlGaN/GaN HEMTs on Si (111), Sapphire, 4H-SiC substrates, various Rapid Thermal Annealing (RTA) conditions for the Ti/Al/Ta/Au ohmic contact process and the resulting surface analysis have been investigated. In order to achieve a low ohmic contact resistance (RC) and a high quality surface morphology, we tested seven steps (800 °C to 920 °C) annealing temperatures and two steps (15, 30 sec) annealing times. According to these annealing temperatures and times, the optimal ohmic resistance of 3.62 × 10-6 Ohm • cm2 on Si(111) substrate, 9.44 × 10-6 Ohm • cm2 on Sapphire substrate and 1.24 × 10-6 Ohm • cm2 on 4H-SiC substrate are obtained at an annealing temperature of 850 °C and an annealing time of 30 sec, 800 °C and an annealing time of 30 sec and 900 °C and an annealing time of 30 sec, respectively. The surface morphologies of the ohmic contact metallization at different annealing temperatures are measured using an Atomic Force Microscope (AFM). AFM morphology Root Mean Square (RMS) level determines the relationship of the annealing temperature and the annealing time for all of the samples. According to these annealing temperatures and times, the optimal ohmic surface RMS roughness of 13.4 nm on Si(111) substrate, 3.8 nm on Sapphire substrate and 2.9 nm on 4H-SiC substrate are obtained at an annealing temperature of 850 °C and an annealing time of 30 sec, 800 °C and an annealing time of 30 sec and 900 °C and an annealing time of 30 sec, respectively.


2018 ◽  
Vol 924 ◽  
pp. 389-392 ◽  
Author(s):  
Mattias Ekström ◽  
Shuoben Hou ◽  
Hossein Elahipanah ◽  
Arash Salemi ◽  
Mikael Östling ◽  
...  

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.


Author(s):  
R. Rajesh ◽  
J. Liu ◽  
H. Fathollahnejad ◽  
R. W. Carpenter ◽  
G. N. Maracas

For the past decade, there has been considerable focus on low resistance Pd-Ge ohmic contacts to GaAs. One approach toward achieving thermodynamically stable ohmic contacts is to consider solid-phasereactions for contacts, rather than the liquid phase interactions that occur upon ohmic alloying of Au-Ge-based systems. The two classifications to this approach are: low temperature annealing (<500°C), mainly using Pd, and high temperature annealing (<500°C), mainly using In. The low temperature annealing class is more compatible with existing GaAs technology, hence the attention to Pd-based systems, particularly Pd-Ge. There has also been tremendous interest in hybrid GaAs-on-Si technology. As an alternative to direct lattice-mismatched growth of GaAs on Si, the epitaxial lift-off (ELO) technique has been used, wherein GaAs devices grown on GaAs substrates can be removed and bonded to any substrate regardless of orientation and/or lattice matching criteria. This process yields high quality dislocation-free GaAs-based devices for hybrid applications.In this study, we demonstrate a low resistance non-alloyed Pd-Ge ohmic contact to epitaxialiy lifted-off n-type GaAs.


2010 ◽  
Vol 43 (39) ◽  
pp. 395102 ◽  
Author(s):  
Rumin Gong ◽  
Jinyan Wang ◽  
Zhihua Dong ◽  
Shenghou Liu ◽  
Min Yu ◽  
...  

2000 ◽  
Vol 88 (1) ◽  
pp. 309-315 ◽  
Author(s):  
Nien-Po Chen ◽  
H. J. Ueng ◽  
D. B. Janes ◽  
J. M. Woodall ◽  
M. R. Melloch

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