A low-power low-voltage slew-rate enhancement circuit for two-stage operational amplifiers

2012 ◽  
Vol 33 (9) ◽  
pp. 095007 ◽  
Author(s):  
Chen Shu ◽  
Jun Xu ◽  
Fan Ye ◽  
Junyan Ren
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Operational Amplifiers ◽  
Slew Rate ◽  
Two Stage ◽  
Rate Enhancement

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

IMPROVED LOW-POWER HIGH-SPEED BUFFER AMPLIFIER WITH SLEW-RATE ENHANCEMENT FOR LCD APPLICATIONS

2010 ◽  
Vol 19 (02) ◽  
pp. 325-334 ◽  
Author(s):  
DAVIDE MARANO ◽  
GAETANO PALUMBO ◽  
SALVATORE PENNISI
Keyword(s):  
Low Power ◽  
High Speed ◽  
Liquid Crystal Display ◽  
Slew Rate ◽  
Output Stage ◽  
Line Load ◽  
Rate Enhancement ◽  
Static Operation ◽  
Limited Power ◽  
Buffer Amplifier

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

A low-power fast transient output capacitor-free adaptively biased LDO based on slew rate enhancement for SoC applications

2015 ◽  
Vol 46 (8) ◽  
pp. 740-749 ◽  
Author(s):  
Chee-Cheow Lim ◽  
Nai-Shyan Lai ◽  
Gim-Heng Tan ◽  
Harikrishnan Ramiah
Keyword(s):  
Low Power ◽  
Slew Rate ◽  
Rate Enhancement ◽  
Fast Transient ◽  
Output Capacitor

A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

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