A QFGMOS-Based gm-Boosted and Adaptively Biased Two-Stage Amplifier Offering Very High Gain and High Bandwidth

2021 ◽  
pp. 2250056
Author(s):  
Urvashi Bansal ◽  
Abhilasha Bakre ◽  
Prem Kumar ◽  
Devansh Yadav ◽  
Mohit Kumar ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Slew Rate ◽  
Two Stage ◽  
Adaptive Biasing ◽  
Unity Gain ◽  
High Bandwidth ◽  
Cmos Amplifier

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4[Formula: see text]MHz and 132[Formula: see text]dB, respectively. The amplifier is operated at 0.6[Formula: see text]V dual supply with 89[Formula: see text][Formula: see text]W power consumption and has a nearly symmetrical average slew rate of 51.5[Formula: see text]V/[Formula: see text]s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

A Low-Noise Biopotential CMOS Amplifier IC Using Low-Power Two-Stage OTA for Neural Recording Applications

2018 ◽  
Vol 27 (05) ◽  
pp. 1850068 ◽  
Author(s):  
Hyung Seok Kim ◽  
Hyouk-Kyu Cha
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Neural Recording ◽  
Open Loop ◽  
Low Noise ◽  
Two Stage ◽  
Prosthetic Devices ◽  
Transconductance Amplifier ◽  
Cmos Amplifier

This work presents a low-power biopotential amplifier integrated circuit (IC) for implantable neural recording prosthetic devices which have been implemented using 0.18-[Formula: see text]m CMOS technology. The proposed neural recording amplifier is based on a capacitive-feedback architecture and utilizes a low-power two-stage source-degenerated operational transconductance amplifier (OTA) with a modified current buffer compensation for large open-loop gain, low-noise and wide bandwidth. The designed amplifier achieves a measured gain of 39.2[Formula: see text]dB with a bandwidth between 0.25[Formula: see text]Hz to 28[Formula: see text]kHz, integrated input referred noise of 5.79[Formula: see text][Formula: see text]Vrms and noise efficiency factor of 3.16. The IC consumes 2.4[Formula: see text][Formula: see text]W at 1.2[Formula: see text]V supply and the die area is 0.09[Formula: see text]mm2.

A High Step-up DC-DC Converter Based on the Voltage Lift Technique for Renewable Energy Applications

2021 ◽  
Vol 13 (19) ◽  
pp. 11059
Author(s):  
Shahrukh Khan ◽  
Arshad Mahmood ◽  
Mohammad Zaid ◽  
Mohd Tariq ◽  
Chang-Hua Lin ◽  
...  
Keyword(s):  
Renewable Energy ◽  
Common Ground ◽  
Closed Loop ◽  
Low Voltage ◽  
Renewable Energy Sources ◽  
Input Voltage ◽  
High Gain ◽  
Boost Converter ◽  
Open Loop ◽  
Voltage Gain

High gain DC-DC converters are getting popular due to the increased use of renewable energy sources (RESs). Common ground between the input and output, low voltage stress across power switches and high voltage gain at lower duty ratios are desirable features required in any high gain DC-DC converter. DC-DC converters are widely used in DC microgrids to supply power to meet local demands. In this work, a high step-up DC-DC converter is proposed based on the voltage lift (VL) technique using a single power switch. The proposed converter has a voltage gain greater than a traditional boost converter (TBC) and Traditional quadratic boost converter (TQBC). The effect of inductor parasitic resistances on the voltage gain of the converter is discussed. The losses occurring in various components are calculated using PLECS software. To confirm the performance of the converter, a hardware prototype of 200 W is developed in the laboratory. The simulation and hardware results are presented to determine the performance of the converter in both open-loop and closed-loop conditions. In closed-loop operation, a PI controller is used to maintain a constant output voltage when the load or input voltage is changed.

scholarly journals A Low-Power, High-Gain Amplifier with Rail-to-Rail Operating Capability: Applications to Biomedical Signal Processing

2021 ◽  
Vol 58 (1) ◽  
pp. 71-76
Author(s):  
Hassan Faraji Baghtash ◽  
Rasoul Pakdel
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Process Variations ◽  
High Gain ◽  
Biomedical Signal Processing ◽  
Noise Power ◽  
Well Performance ◽  
Subthreshold Region ◽  
Rail To Rail ◽  
Unity Gain

low-voltage, low-power, rail-to-rail, two-stage trans-conductance amplifier is presented. The structure exploits body-driven transistors, configured in folded-cascode structure. To reduce the power consumption, the transistors are biased in the subthreshold region. The Specter RF simulation results which are conducted in TSMC 180nm CMOS standard process proves the well-performance of the proposed structure. The performance of the proposed structure against process variations is checked through process corners and Monte Carlo simulations. The results prove the robustness of the proposed amplifier against process uncertainties. Some important specifications of the design derived from circuit simulations are 93.36 dB small-signal gain, 14.4 PV2/Hz input referred noise power, 26.5 kHz unity gain frequency, 20 V/ms slew rate. The proposed structure draws 260 nW power from 0.5 V power supply and is loaded with a 15 pF loading capacitor. The input common mode range of structure is from 0 to 0.5 V.

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

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