Fabrication and Device Simulation of Single Nano-Scale Organic Static Induction Transistors

2006 ◽  
Vol E89-C (12) ◽  
pp. 1765-1770 ◽  
Author(s):  
N. OHASHI ◽  
M. NAKAMURA ◽  
N. MURAISHI ◽  
M. SAKAI ◽  
K. KUDO
Keyword(s):  
Device Simulation ◽  
Nano Scale ◽  
Static Induction Transistors ◽  
Static Induction

Three Dimensional Analysis of Turnoff Operation of SiC Buried Gate Static Induction Transistors (BG-SITs)

2008 ◽  
Vol 600-603 ◽  
pp. 1075-1078 ◽  
Author(s):  
Koji Yano ◽  
Yasunori Tanaka ◽  
Tsutomu Yatsuo ◽  
Akio Takatsuka ◽  
Mitsuo Okamoto ◽  
...  
Keyword(s):  
Initial Phase ◽  
Three Dimensional ◽  
Device Simulation ◽  
Displacement Current ◽  
Current Crowding ◽  
Static Induction Transistors ◽  
Static Induction ◽  
The Impact ◽  
Channel Center ◽  
A Current

The turnoff mechanism of SiC buried gate static induction transistors (SiC-BGSITs) were analyzed by three dimensional device simulation. A current crowding occurs in the portion near the channel center away from the gate contact during the initial phase of the turnoff operation, which is resulted from a non-uniform potential distribution through the gate finger with the displacement current flowing there. This increases the turnoff delay time. The impact of source length on the turnoff performance was made clear.

3 kV Normally-Off 4H-SiC Buried Gate Static Induction Transistors (SiC-BGSITs)

2014 ◽  
Vol 778-780 ◽  
pp. 899-902 ◽  
Author(s):  
Akio Takatsuka ◽  
Yasunori Tanaka ◽  
Koji Yano ◽  
Norio Matsumoto ◽  
Tsutomu Yatsuo ◽  
...  
Keyword(s):  
Leakage Current ◽  
Leakage Current Density ◽  
Current Density ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Fabrication Process ◽  
Drain Voltage ◽  
Static Induction Transistors ◽  
Static Induction

3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm2, compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm2.

Experimental Study of Short-Circuit Capability of Normally-off SiC-BGSITs

2013 ◽  
Vol 740-742 ◽  
pp. 962-965
Author(s):  
Akio Takatsuka ◽  
Yasunori Tanaka ◽  
Koji Yano ◽  
Tsutomu Yatsuo ◽  
Kazuo Arai
Keyword(s):  
Experimental Study ◽  
Short Circuit ◽  
Static Induction Transistors ◽  
Static Induction

We investigated the short-circuit capabilities of 1.2 kV normally-off SiC buried gate static induction transistors (SiC-BGSITs). The maximum short-circuit energy was found to be 35.6 J/cm2, which is twice that of normally-on SiC-BGSITs and 3.3–5.6 times higher than that of the Si-IGBTs. The maximum short-circuit time was 590 μs. It is concluded that these high short-circuit capabilities result from saturation characteristics of the normally-off SiC-BGSITs.

scholarly journals Modeling of a GaN Based Static Induction Transistor

1999 ◽  
Vol 4 (S1) ◽  
pp. 697-702 ◽  
Author(s):  
Gabriela E. Bunea ◽  
S.T. Dunham ◽  
T.D. Moustakas
Keyword(s):  
Operating Conditions ◽  
Short Channel ◽  
Flow Equations ◽  
Static Induction Transistors ◽  
Thermal Boundary Conditions ◽  
Heating Effects ◽  
Device Structures ◽  
Static Induction Transistor ◽  
Static Induction ◽  
Voltage Swing

Static induction transistors (SITs) are short channel FET structures which are suitable for high power, high frequency and high temperature applications. GaN has particularly favorable properties for SIT operation. However, such a device has not yet been fabricated. In this paper we report simulation studies on GaN static induction transistors over a range of device structures and operating conditions. The transistor was modeled with coupled drift-diffusion and heat-flow equations. We found that the performance of the device depends sensitively on the thermal boundary conditions, as self-heating effects limit the maximum voltage swing.

Simple Self-Aligned Fabrication Process for Silicon Carbide Static Induction Transistors

2004 ◽  
Vol 457-460 ◽  
pp. 1125-1128
Author(s):  
K. Dynefors ◽  
V. Desmaris ◽  
Joakim Eriksson ◽  
Per Åke Nilsson ◽  
Niklas Rorsman ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Fabrication Process ◽  
Static Induction Transistors ◽  
Static Induction
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