An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter

2007 ◽  
Vol E90-C (6) ◽  
pp. 1197-1202
Author(s):  
S. DOSHO ◽  
N. YANAGISAWA ◽  
K. SOGAWA ◽  
Y. YAMADA ◽  
T. MORIE
Keyword(s):  
Adaptive Control ◽  
Phase Locked Loop ◽  
Switched Capacitor ◽  
Loop Filter ◽  
Control Phase ◽  
Wide Range

scholarly journals A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

2021 ◽  
Author(s):  
Baoling Guo ◽  
Seddik Bacha ◽  
Mazen Alamir ◽  
Julien Pouget
Keyword(s):  
Performance Analysis ◽  
Frequency Domain ◽  
Low Frequency ◽  
Experimental Tests ◽  
Frequency Measurement ◽  
Phase Locked Loop ◽  
Frequency Domain Analysis ◽  
Loop Filter ◽  
Control Stability ◽  
Unbalanced Grid

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.

A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector

2018 ◽  
Vol 53 (1) ◽  
pp. 50-65 ◽  
Author(s):  
Taekwang Jang ◽  
Seokhyeon Jeong ◽  
Dongsuk Jeon ◽  
Kyojin David Choo ◽  
Dennis Sylvester ◽  
...  
Keyword(s):  
Phase Locked Loop ◽  
Switched Capacitor ◽  
Digital Phase

Design of high-frequency wide-range all digital phase locked loop in 90 nm CMOS

2013 ◽  
Vol 75 (1) ◽  
pp. 133-145 ◽  
Author(s):  
Prashanth Muppala ◽  
Saiyu Ren ◽  
George Yu-Heng Lee
Keyword(s):  
High Frequency ◽  
Phase Locked Loop ◽  
Digital Phase ◽  
Wide Range

Design and performance study of phase-locked loop using fractional-order loop filter

2014 ◽  
Vol 43 (6) ◽  
pp. 776-792 ◽  
Author(s):  
Madhab Chandra Tripathy ◽  
Debasmita Mondal ◽  
Karabi Biswas ◽  
Siddhartha Sen
Keyword(s):  
Fractional Order ◽  
Phase Locked Loop ◽  
Performance Study ◽  
Loop Filter ◽  
And Performance

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

Single Phase Variable Sampling Phase Locked Loop using Composite Observer

2016 ◽  
Vol 2 (1) ◽  
pp. 49
Author(s):  
K Arun ◽  
K Selvajyothi
Keyword(s):  
Sampling Period ◽  
Phase Locked Loop ◽  
Pole Placement ◽  
Phase Variable ◽  
Variable Sampling ◽  
Drift Frequency ◽  
Wide Range ◽  
Periodic Input ◽  
The Stability ◽  
Placement Technique

<p>An observer based variable sampling period phase locked loop is introduced for grid connected systems. The composite observer acts as an efficient estimator of the fundamental components from a periodic input signal rich in DC and harmonics. The observer gains are designed using pole placement technique, which inherently ensures the stability of this estimator.  Even under drift frequency, a constant number of samples (512) per cycle are maintained with the help of the numerically controlled oscillator. This makes the oscillator gain elements in the observer a constant and eliminates the trigonometric computation. This phase locked loop is found to be working in a wide range of frequency 40 – 70Hz. The performance of the proposed scheme is studied with a synthetic harmonic rich signal as well as validated by implementing the PLL in Cyclone IV FPGA with a real time grid voltage.</p>

scholarly journals X-Type Step-Up Multi-Level Inverter with Reduced Component Count Based on Switched-Capacitor Concept

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 1987
Author(s):  
Erfan Azimi ◽  
Aryorad Khodaparast ◽  
Mohammad Javad Rostami ◽  
Jafar Adabi ◽  
M. Ebrahim Adabi ◽  
...  
Keyword(s):  
Power Flow ◽  
Input Voltage ◽  
Switching Frequency ◽  
Switched Capacitor ◽  
Level Control ◽  
Voltage Balancing ◽  
Simulink Model ◽  
Wide Range ◽  
Multi Level ◽  
Laboratory Prototype

This paper aims to present a novel switched-capacitor multi-level inverter. The presented structure generates a staircase near sinusoidal AC voltage by using a single DC source and a few capacitors to step-up the input voltage. The nearest level control (NLC) strategy is used to control the operation of the converter. These switching states are designed in a way that they always ensure the self-voltage balancing of the capacitors. Low switching frequency, simple control, and inherent bipolar output are some of the advantages of the presented inverter. Compared to other existing topologies, the structure requires fewer circuit elements. Bi-directional power flow ability of the proposed topology, facilitates the operation of the circuit under wide range of load behaviors which makes it applicable in most industries. Besides, a 13-level laboratory prototype is implemented to realize and affirm the efficacy of the MATLAB Simulink model under different load conditions. The simulation and experimental results accredit the appropriate performance of the converter. Finally, a theoretical efficiency of 92.73% is reached.

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