Solder joint defect classification based on ensemble learning

2017 ◽  
Vol 29 (3) ◽  
pp. 164-170 ◽  
Author(s):  
Hao Wu

Purpose This paper aims to inspect the defects of solder joints of printed circuit board in real-time production line, simple computing and high accuracy are primary consideration factors for feature extraction and classification algorithm. Design/methodology/approach In this study, the author presents an ensemble method for the classification of solder joint defects. The new method is based on extracting the color and geometry features after solder image acquisition and using decision trees to guarantee the algorithm’s running executive efficiency. To improve algorithm accuracy, the author proposes an ensemble method of random forest which combined several trees for the classification of solder joints. Findings The proposed method has been tested using 280 samples of solder joints, including good and various defect types, for experiments. The results show that the proposed method has a high accuracy. Originality/value The author extracted the color and geometry features and used decision trees to guarantee the algorithm's running executive efficiency. To improve the algorithm accuracy, the author proposes using an ensemble method of random forest which combined several trees for the classification of solder joints. The results show that the proposed method has a high accuracy.

2017 ◽  
Vol 29 (4) ◽  
pp. 199-202 ◽  
Author(s):  
Fang Liu ◽  
Jiacheng Zhou ◽  
Nu Yan

Purpose The purpose of this paper is to study the drop reliability of ball-grid array (BGA) solder joints affected by thermal cycling. Design/methodology/approach The drop test was made with the two kinds of chip samples with the thermal cycling or not. Then, the dyeing process was taken by these samples. Finally, through observing the metallographic analysis results, the conclusions could be found. Findings It is observed that the solder joint cracks which were only subjected to drop loads without thermal cycling appeared near the BGA package pads. The solder joint cracks which were subjected to drop loads with thermal cycling appear near the printed circuit board pads. Originality/value This paper obtains the solder joint cracks picture with drop test under the thermal cycling.


2015 ◽  
Vol 27 (1) ◽  
pp. 52-58 ◽  
Author(s):  
Peter K. Bernasko ◽  
Sabuj Mallik ◽  
G. Takyi

Purpose – The purpose of this paper is to study the effect of intermetallic compound (IMC) layer thickness on the shear strength of surface-mount component 1206 chip resistor solder joints. Design/methodology/approach – To evaluate the shear strength and IMC thickness of the 1206 chip resistor solder joints, the test vehicles were conventionally reflowed for 480 seconds at a peak temperature of 240°C at different isothermal ageing times of 100, 200 and 300 hours. A cross-sectional study was conducted on the reflowed and aged 1206 chip resistor solder joints. The shear strength of the solder joints aged at 100, 200 and 300 hours was measured using a shear tester (Dage-4000PXY bond tester). Findings – It was found that the growth of IMC layer thickness increases as the ageing time increases at a constant temperature of 175°C, which resulted in a reduction of solder joint strength due to its brittle nature. It was also found that the shear strength of the reflowed 1206 chip resistor solder joint was higher than the aged joints. Moreover, it was revealed that the shear strength of the 1206 resistor solder joints aged at 100, 200 and 300 hours was influenced by the ageing reaction times. The results also indicate that an increase in ageing time and temperature does not have much influence on the formation and growth of Kirkendall voids. Research limitations/implications – A proper correlation between shear strength and fracture mode is required. Practical implications – The IMC thickness can be used to predict the shear strength of the component/printed circuit board pad solder joint. Originality/value – The shear strength of the 1206 chip resistor solder joint is a function of ageing time and temperature (°C). Therefore, it is vital to consider the shear strength of the surface-mount chip component in high-temperature electronics.


2019 ◽  
Vol 16 (1) ◽  
pp. 13-20
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
Reza Ghaffarian

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.


Author(s):  
Lei Huang ◽  
Shibin Shen ◽  
Fei Xie ◽  
Jing Zhao ◽  
Jianing Han ◽  
...  

To prevent any negative electromagnetic influence of high-density integrated circuits, an insulation package needs to be specially designed to shield it. Aiming at the low efficiency and material waste in traditional packaging methods, a printed circuit board (PCB) selective packaging system based on a multi-pattern solder joint simultaneous segmentation algorithm and three-dimensional printing technology is introduced in this paper. Firstly, the structure of PCB selective packaging system is designed. Secondly, to solve the existing problems, such as multi-pattern solder joints which are located densely in small welding areas and are hard to be extracted in the small-area integrated circuit board, a multi-pattern solder joint simultaneous segmentation algorithm is developed based on (geometrical) neighborhood features to extract and locate the optimal PCB solder joint areas. Finally, tests using three actual PCB are carried out to compare the proposed method with traditional multi-threshold solder joint extraction methods. Test results indicate that the proposed algorithm is simple and effective. Diverse solder joints can be optimally located and simultaneously extracted from the collected PCB image, which greatly improves the filling rate of the solder joint areas and filters out false pixels. Thus, this method provides a reliable location-finding tool to help place solder points in PCB selective packaging systems.


2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.


Author(s):  
C.L.S.C. Fonseka ◽  
J.A.K.S. Jayasinghe

Purpose: Automatic Optical Inspection (AOI) systems, used in electronics industry have been primarily developed to inspect soldering defects of Surface Mount Devices (SMD) on a Printed Circuit Board (PCB). However, no commercially available AOI system exists that can be integrated to a desktop soldering robotic system, which is capable of identifying soldering defects of Through Hole Technology (THT) solder joints along with the soldering process. In our research, we have implemented an AOI platform that is capable of performing automatic quality assurance of THT solder joints in a much efficient way. In this paper, we have presented a novel approach to identify soldering defects of THT solder joints, based on the location of THT component lead top. This paper presents the methodologies that can be used to precisely identify and localize THT component lead inside a solder joint. Design/methodology/approach: We have discussed the importance of lead top localization and presented a detailed description on the methodologies that can be used to precisely segment and localize THT lead top inside the solder joint. Findings: It could be observed that the precise localization of THT lead top makes the soldering quality assurance process more accurate. A combination of template matching algorithms and colour model transformation provide the most accurate outcome in localizing the component lead top inside solder joint, according to the analysis carried out in this paper. Research limitations/implications: When the component lead top is fully covered by the soldering, the implemented methodologies will not be able to identify the actual location of it. In such a case, if the segmented and detected lead top locations are different, a decision is made based on the direction in which the solder iron tip touches the solder pad. Practical implications: The methodologies presented in this paper can be effectively used to have a precise localization of component lead top inside the solder joint. The precise identification of component lead top leads to have a very precise quality assurance capability to the implemented AOI system. Originality/value: This research proposes a novel approach to identify soldering defects of THT solder joints in a much efficient way based on the component lead top. The value of this paper is quite high, since we have taken all the possibilities that may appear on a solder joint in a practical environment.


Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.


2010 ◽  
Vol 7 (1) ◽  
pp. 13-30 ◽  
Author(s):  
Zhou Zeng ◽  
Zhuang Li ◽  
Zuoyong Zheng

This paper investigates methodologies for locating and identifying the components on a printed circuit board (PCB) used for surface mount device inspection. The proposed scheme consists of two stages: solder joint extraction and protective coating extraction. Solder joints are extracted by first detecting all the highlight areas, and then recognizing and removing the invalid highlight areas which are mainly markings and via-holes. We sum up three color distribution features. And the invalid highlight areas are recognized and removed by comparing the features of the target objects and the reference objects. The sequence of color distribution as a new clue has been applied to clustering solder joints. Each protective coating is extracted by the positions of the clustered solder joints. Experimental results show that the proposed method can extract most of components effectively.


2019 ◽  
Vol 31 (3) ◽  
pp. 181-191 ◽  
Author(s):  
Maciej Sobolewski ◽  
Barbara Dziurdzia

Purpose The purpose of the paper is to experimentally evaluate the impact of voids on thermal conductivity of a macro solder joint formed between a copper cylinder and a copper plate by using reflow soldering. Design/methodology/approach A model of a surface mount device (SMD) was developed in the shape of a cylinder. A copper plate works as a printed circuit board (PCB). The resistor was connected to a power supply and the plate was cooled by a heat sink and a powerful fan. A macro solder joint was formed between a copper cylinder and a copper plate using reflow soldering and a lead-free solder paste SAC305. The solder paste was printed on a plate through stencils of various apertures. It was expected that various apertures of stencils will moderate the various void contents in solder joints. K-type thermocouples mounted inside cylinders and at the bottom of a plate underneath the cylinders measured the temperature gradient on both sides of the solder joint. After finishing the temperature measurements, the cylinders were thinned by milling to thickness of about 2 mm and then X-ray images were taken to evaluate the void contents. Finally the tablets were cross-sectioned to enable scanning electron microscopy (SEM) observations. Findings There was no clear dependence between thermal conductivity of solder joints and void contents. The authors state that other factors such as intermetallic layers, microcracks, crystal grain morfologyof the interface between the solder and the substrate influence on thermal conductivity. To support this observation, further investigations using metallographic methods are required. Originality/value Results allow us to assume that the use of SAC305 alloy for soldering of components with high thermal loads is risky. The common method for thermal balance calculation is based on the sum of serial thermal resistances of mechanical compounds. For these calculations, solder joints are represented with bulk SAC305 thermal conductivity parameters. Thermal conductivity of solder joints for high density of thermal energy is much lower than expected. Solder joints’ structure is not fully comparable with bulk SAC305 alloy. In experiments, the average value of the solder joint conductivity was found to be 8.1 W/m·K, which is about 14 per cent of the nominal value of SAC305 thermal conductivity.


Author(s):  
Zhengfang Qian ◽  
Xin Wu

This paper presents an approach and its demonstration for seamless tool integration for the virtual qualification and reliability prediction of solder joints of surface mounted electronic components on a populated circuit board. Starting from software called Surface Evolver, it can be used to realistically reproduce complicated geometry profiles of solder joints with various lead frames and pad specifications. User routines have been developed under ANSYS platform for automatic geometry transfer from the Surface Evolver and mesh regeneration of the solder joints inside ANSYS, as demonstrated in this paper. Moreover, a number of electronic packages with their solder joints on a typical printed circuit board (PCB) were also regenerated with parametric capability. Finite element analyses (FEAs) with proper set-up of materials, boundary conditions, and constitutive models were performed automatically by hitting one-button to go. Reliability prediction of solder joints and the failure rate of electronic components can be predicted based on failure criteria and test data implemented. An in-house tool was developed for the whole procedure of solder joint qualification and reliability assessment from deterministic to statistical aspects, including the evaluation of defect impacts.


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