scholarly journals Elevated Standoff Heights of Solder Joint Interconnections Can Result in Appreciable Stress and Warpage Relief

2019 ◽  
Vol 16 (1) ◽  
pp. 13-20
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
Reza Ghaffarian
Keyword(s):  
Solder Joint ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Calculated Data ◽  
Circuit Board ◽  
Stress Model ◽  
Solder Material ◽  
The Difference ◽  
Ic Package

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of Integrated Circuit (IC) packages with conventional (small) standoff heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: attributes of the manufacturing process, solder material properties, and design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the Printed Circuit Board (PCB)-package assembly and particularly by the differences in the thermally induced curvatures of the PCB and the package. In this analysis, the stress and warpage issue is addressed using an analytical predictive stress model. The model is a modification and an extension of the model developed back in 1980s by the first author. It is assumed that it is the difference in the postfabrication deflections of the PCB-package assembly that is the root cause of the solder material failures and particularly and perhaps the HnP defects. The calculated data based on the developed stress model suggest that the replacement of the conventional ball grid array (BGA) designs with designs with elevated standoff heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design, referred to as BGA, and a design with solder joints with elevated standoff heights, referred to as column grid array (CGA), are compared. The computed data indicated that the effective stress in the solder material was relieved by about 40% and the difference between the maximum deflections of the PCB and the package was reduced by about 60%, when the BGA design was replaced by a CGA system. Although no definite proof that the use of solder joints with elevated standoff heights will lessen the package propensity to the HnP defects is provided, the authors nonetheless think that there is a reason to believe that the application of solder joints with elevated standoff heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.

Elevated Stand-Off Heights in Solder Joint Interconnections of Surface Mounted IC Packages Result in Appreciable Stress and Warpage Relief

2018 ◽  
Vol 2018 (1) ◽  
pp. 000534-000542
Author(s):  
Ephraim Suhir ◽  
Sung Yi ◽  
Jennie S. Hwang ◽  
R. Ghaffarian
Keyword(s):  
Solder Joint ◽  
Solder Joints ◽  
Calculated Data ◽  
Ball Grid Array ◽  
Substantial Improvement ◽  
Stress Model ◽  
Solder Material ◽  
The Difference ◽  
Free Solder ◽  
Ic Package

Abstract The “head-in-pillow” (HnP) defects in lead-free solder joint interconnections of IC packages with conventional (small) stand-off heights of the solder joints, and particularly in packages with fine pitches, are attributed by many electronic material scientists to the three major causes: 1) attributes of the manufacturing process, 2) solder material properties and 3)design-related issues. The latter are thought to be caused primarily by elevated stresses in the solder material, as well as by the excessive warpage of the PCB-package assembly and particularly to the differences in the thermally induced curvatures of the PCB and the package. In this analysis the stress-and-warpage issue is addressed using an analytical predictive stress model. This model is a modification and an extension of the model developed back in 1980-s by the first author. It is assumed that it is the difference in the post-fabrication deflections of the PCB-package assembly that is the root cause of the solder materials failures and particularly and perhaps the HnP defects. The calculated data based on the developed analytical thermal stress model suggest that the replacement of the conventional ball-grid-array (BGA) designs with designs characterized by elevated stand-off heights of the solder joints could result in significant stress and warpage relief and, hopefully, in a lower propensity of the IC package to HnP defects as well. The general concepts are illustrated by a numerical example, in which the responses to the change in temperature of a conventional design referred to as ball-grid-array (BGA) and a design with solder joints with elevated stand-off heights referred to as column-grid-array (CGA) are compared. The computed data indicated that the effective stress in the solder material is relieved by about 40% and the difference between the maximum deflections of the PCB and the package is reduced by about 60%, when the BGA design is replaced by a CGA system. Although no proof that the use of solder joints with elevated stand-off heights will lessen the package propensity to the HnP defects is provided, the authors think that there is a reason to believe that the application of solder joints with elevated stand-off heights could result in a substantial improvement in the general IC package performance, including, perhaps, its propensity to HnP defects.

scholarly journals A Novel Multi-Pattern Solder Joint Simultaneous Segmentation Algorithm for PCB Selective Packaging Systems

2019 ◽  
Vol 33 (13) ◽  
pp. 2058005
Author(s):  
Lei Huang ◽  
Shibin Shen ◽  
Fei Xie ◽  
Jing Zhao ◽  
Jianing Han ◽  
...  
Keyword(s):  
Solder Joint ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Extraction Methods ◽  
Segmentation Algorithm ◽  
Circuit Board ◽  
Packaging System ◽  
Low Efficiency

To prevent any negative electromagnetic influence of high-density integrated circuits, an insulation package needs to be specially designed to shield it. Aiming at the low efficiency and material waste in traditional packaging methods, a printed circuit board (PCB) selective packaging system based on a multi-pattern solder joint simultaneous segmentation algorithm and three-dimensional printing technology is introduced in this paper. Firstly, the structure of PCB selective packaging system is designed. Secondly, to solve the existing problems, such as multi-pattern solder joints which are located densely in small welding areas and are hard to be extracted in the small-area integrated circuit board, a multi-pattern solder joint simultaneous segmentation algorithm is developed based on (geometrical) neighborhood features to extract and locate the optimal PCB solder joint areas. Finally, tests using three actual PCB are carried out to compare the proposed method with traditional multi-threshold solder joint extraction methods. Test results indicate that the proposed algorithm is simple and effective. Diverse solder joints can be optimally located and simultaneously extracted from the collected PCB image, which greatly improves the filling rate of the solder joint areas and filters out false pixels. Thus, this method provides a reliable location-finding tool to help place solder points in PCB selective packaging systems.

Solder joint defect classification based on ensemble learning

2017 ◽  
Vol 29 (3) ◽  
pp. 164-170 ◽  
Author(s):  
Hao Wu
Keyword(s):  
Random Forest ◽  
Solder Joint ◽  
Decision Trees ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
High Accuracy ◽  
Ensemble Method ◽  
Circuit Board ◽  
Content Type

Purpose This paper aims to inspect the defects of solder joints of printed circuit board in real-time production line, simple computing and high accuracy are primary consideration factors for feature extraction and classification algorithm. Design/methodology/approach In this study, the author presents an ensemble method for the classification of solder joint defects. The new method is based on extracting the color and geometry features after solder image acquisition and using decision trees to guarantee the algorithm’s running executive efficiency. To improve algorithm accuracy, the author proposes an ensemble method of random forest which combined several trees for the classification of solder joints. Findings The proposed method has been tested using 280 samples of solder joints, including good and various defect types, for experiments. The results show that the proposed method has a high accuracy. Originality/value The author extracted the color and geometry features and used decision trees to guarantee the algorithm's running executive efficiency. To improve the algorithm accuracy, the author proposes using an ensemble method of random forest which combined several trees for the classification of solder joints. The results show that the proposed method has a high accuracy.

scholarly journals Study on the Impact of Lead Sidewall Solder Coverage and Corner Lead Size on Joint Reliability

2021 ◽  
pp. 62-69
Author(s):  
Jefferson Talledo
Keyword(s):  
Solder Joint ◽  
Integrated Circuit ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Solder Fatigue ◽  
The Impact

Solder joint reliability is very important to ensure that an integrated circuit (IC) semiconductor package is functional within its intended life span as the solder joint establishes electrical connection between the IC and the printed circuit board (PCB). Solder fatigue failure or crack under thermal cycling is one of the common problems with board-mounted packages. There are several factors or package characteristics that have impact on solder fatigue life like package size and material properties of the package components. This paper presents a thermo-mechanical modeling of a leadframe-based semiconductor package to study the impact of lead sidewall solder coverage and corner lead size on the solder joint reliability. Finite element analysis (FEA) technique was used to calculate the solder life considering 50% and 100% package lead sidewall solder coverage as well as smaller and larger critical corner leads of the package. The results of the analysis showed that higher lead sidewall solder coverage and larger lead could significantly increase solder life. Therefore, ensuring lead sidewall solder wettability to have higher solder coverage is beneficial. The study also reveals that packages with side wettable flanks are not only enabling high speed automated optical inspection required for the automotive industry, but they are also providing improved solder joint reliability.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

2012 ◽  
Vol 2012 (1) ◽  
pp. 001038-001045 ◽  
Author(s):  
Sheng-Tsai Wu ◽  
John H. Lau ◽  
Heng-Chieh Chien ◽  
Yu-Lin Chao ◽  
Ra-Min Tain ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Creep Strain ◽  
High Power ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Random Access ◽  
Circuit Board ◽  
3D Ic ◽  
Silicon Vias

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

Creep-caused fracture of PbSn solder joint

2017 ◽  
Vol 31 (16-19) ◽  
pp. 1744008
Author(s):  
M. Meng ◽  
Z. B. Wang ◽  
X. Wang ◽  
Y. Chen
Keyword(s):  
Solder Joint ◽  
Failure Analysis ◽  
Stress Level ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Fracture Morphology ◽  
Circuit Board ◽  
Electronic Assembly ◽  
Printed Circuit ◽  
Pbsn Solder

This paper analyzes two failure cases of creep-caused fracture of PbSn solder joint, including the joint between the wire and solder cup in the connector and the joint between the integrated circuit (IC) pins and the printed circuit board (PCB). The environment conditions, for the creep of PbSn solder joint is demonstrated, including the temperature and stress level. The stress origin and fracture morphology are summarized based on the failure analysis. Besides, the developing process of creep-caused fracture is explained. The paper comprehensively clarifies the creep mechanism of PbSn solder and consequently provides significant guidance for the reliable electronic assembly to avoid the creep-caused damage.

Modeling and Simulation of PCB Assembly under Board-Level Drop Impact

2010 ◽  
Vol 34-35 ◽  
pp. 451-455
Author(s):  
Fang Liu ◽  
Guang Meng
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Fe Model ◽  
Fe Method ◽  
Acceleration Pulse ◽  
Pcb Assembly ◽  
Free Solder ◽  
Board Level

Finite element (FE) method is an efficient and power tool, and is adopted to analyze dynamic response of printed circuit board (PCB) assembly. First, FE model of PCB assembly was established. Second, the dynamic behaviors of ball gird array (BGA) lead-free solder joint were obtained when the PCB assembly was subjected to a half-sine acceleration pulse. Results show that the maximum tensile stresses occur at solder joints located at the four outermost corners of BGA and solder joints at outermost corners are the most vulnerable to crack. In addition, it can be found during FE analysis that the solder joint reliability can be enhanced as the PCB damping increases and input acceleration level reduces.

Localization of component lead inside a THT solder joint for solder defects classification

2017 ◽  
Vol 2 (83) ◽  
pp. 57-66 ◽  
Author(s):  
C.L.S.C. Fonseka ◽  
J.A.K.S. Jayasinghe
Keyword(s):  
Quality Assurance ◽  
Solder Joint ◽  
Template Matching ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Precise Localization ◽  
Soldering Process ◽  
Novel Approach ◽  
Defects Classification

Purpose: Automatic Optical Inspection (AOI) systems, used in electronics industry have been primarily developed to inspect soldering defects of Surface Mount Devices (SMD) on a Printed Circuit Board (PCB). However, no commercially available AOI system exists that can be integrated to a desktop soldering robotic system, which is capable of identifying soldering defects of Through Hole Technology (THT) solder joints along with the soldering process. In our research, we have implemented an AOI platform that is capable of performing automatic quality assurance of THT solder joints in a much efficient way. In this paper, we have presented a novel approach to identify soldering defects of THT solder joints, based on the location of THT component lead top. This paper presents the methodologies that can be used to precisely identify and localize THT component lead inside a solder joint. Design/methodology/approach: We have discussed the importance of lead top localization and presented a detailed description on the methodologies that can be used to precisely segment and localize THT lead top inside the solder joint. Findings: It could be observed that the precise localization of THT lead top makes the soldering quality assurance process more accurate. A combination of template matching algorithms and colour model transformation provide the most accurate outcome in localizing the component lead top inside solder joint, according to the analysis carried out in this paper. Research limitations/implications: When the component lead top is fully covered by the soldering, the implemented methodologies will not be able to identify the actual location of it. In such a case, if the segmented and detected lead top locations are different, a decision is made based on the direction in which the solder iron tip touches the solder pad. Practical implications: The methodologies presented in this paper can be effectively used to have a precise localization of component lead top inside the solder joint. The precise identification of component lead top leads to have a very precise quality assurance capability to the implemented AOI system. Originality/value: This research proposes a novel approach to identify soldering defects of THT solder joints in a much efficient way based on the component lead top. The value of this paper is quite high, since we have taken all the possibilities that may appear on a solder joint in a practical environment.

scholarly journals The Effect of Epoxy Polymer Addition in Sn-Ag-Cu and Sn-Bi Solder Joints

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 960 ◽  
Author(s):  
Min-Soo Kang ◽  
Do-Seok Kim ◽  
Young-Eui Shin
Keyword(s):  
Solder Joint ◽  
Strain Energy ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Solder Paste ◽  
Element Analysis ◽  
Printed Circuit ◽  
Shock Testing ◽  
Polymer Addition

To analyze the reinforcement effect of adding polymer to solder paste, epoxies were mixed with two currently available Sn-3.0Ag-0.5Cu (wt.% SAC305) and Sn-59Bi (wt.%) solder pastes and specimens prepared by bonding chip resistors to a printed circuit board. The effect of repetitive thermal stress on the solder joints was then analyzed experimentally using thermal shock testing (−40 °C to 125 °C) over 2000 cycles. The viscoplastic stress–strain curves generated in the solder were simulated using finite element analysis, and the hysteresis loop was calculated. The growth and propagation of cracks in the solder were also predicted using strain energy formulas. It was confirmed that the epoxy paste dispersed the stress inside the solder joint by externally supporting the solder fillet, and crack formation was suppressed, improving the lifetime of the solder joint.

Thermal cycling effect on the drop reliability of BGA lead-free solder joints

2017 ◽  
Vol 29 (4) ◽  
pp. 199-202 ◽  
Author(s):  
Fang Liu ◽  
Jiacheng Zhou ◽  
Nu Yan
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Drop Test ◽  
Circuit Board ◽  
Metallographic Analysis ◽  
Content Type ◽  
Bga Package ◽  
Free Solder

Purpose The purpose of this paper is to study the drop reliability of ball-grid array (BGA) solder joints affected by thermal cycling. Design/methodology/approach The drop test was made with the two kinds of chip samples with the thermal cycling or not. Then, the dyeing process was taken by these samples. Finally, through observing the metallographic analysis results, the conclusions could be found. Findings It is observed that the solder joint cracks which were only subjected to drop loads without thermal cycling appeared near the BGA package pads. The solder joint cracks which were subjected to drop loads with thermal cycling appear near the printed circuit board pads. Originality/value This paper obtains the solder joint cracks picture with drop test under the thermal cycling.

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