Ultra-low dc power GaAs HBT S- and C-band low noise amplifiers for portable wireless applications

1995 ◽  
Vol 43 (12) ◽  
pp. 3055-3061 ◽  
Author(s):  
K.W. Kobayashi ◽  
A.K. Oki ◽  
L.T. Tran ◽  
D.C. Streit
Keyword(s):  
Low Noise ◽  
Low Noise Amplifiers ◽  
Wireless Applications ◽  
Dc Power

Ka-band monolithic GaAs PHEMT low-noise amplifiers for commercial wireless applications

1999 ◽  
Author(s):  
Huei Wang ◽  
Tzu-Hung Chen ◽  
D.C. Niu ◽  
Yi-Jen Chan ◽  
P.W. Kuo ◽  
...  
Keyword(s):  
Low Noise ◽  
Low Noise Amplifiers ◽  
Ka Band ◽  
Wireless Applications

Extrinsic and Intrinsic Modeling of InGaAs/InAlAs pHEMT for Wireless Applications

2015 ◽  
Vol 815 ◽  
pp. 369-373
Author(s):  
Norhawati Ahmad ◽  
S.S. Jamuar ◽  
M. Mohammad Isa ◽  
Siti Salwa Mat Isa ◽  
Muhammad Mahyiddin Ramli ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
High Electron Mobility Transistors ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
High Electron ◽  
Wireless Applications ◽  
Electron Mobility Transistors ◽  
Low Leakage ◽  
The University ◽  
University Of Manchester

This paper presents the linear modelling of high breakdown InP pseudomorphic High Electron Mobility Transistors (pHEMT) that have been developed and fabricated at the University of Manchester (UoM) for low noise applications mainly for the Square Kilometre Array (SKA) project. The ultra-low leakage properties of a novel InGaAs/InAlAs/InP pHEMTs structure were used to fabricate a series of transistor with total gate width ranging from 0.2 mm to 1.2 mm. The measured DC and S-Parameters data from the fabricated devices were then used for the transistors’ modelling. The transistors demonstrated to operate up to frequencies of 25 GHz. These transistors models are used in the design of Low Noise Amplifiers (LNAs) using fully Monolithic Microwave Integrated Circuit (MMIC) technology.

scholarly journals Design and Analysis of Cascode LNA for 60 GHz Wireless Applications

2019 ◽  
Vol 8 (9) ◽  
pp. 1399-1403
Keyword(s):  
Power Dissipation ◽  
Design Methodology ◽  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
60 Ghz ◽  
Unconditionally Stable ◽  
Wireless Applications ◽  
Dc Power ◽  
Noise Amplifier

Design methodology and analysis of a 60GHz-band Low Noise Amplifier (LNA) is presented in this paper. The LNA has been designed and simulated using source degenerated cascode topology in 90 nm CMOS for operation at 60 GHz. The structured LNA is minimized for its area with 50%. The designed LNA is computed with ADS and is verified its functionality in terms of Noise Figure (NF), Gain, Linearity, Power dissipation and Stability. The designed LNA uses 12 mW of dc power from a 1.5 V supply with 16.3 dB gain and a NF of 3.5 dB at 60 GHz. The designed LNA is unconditionally stable and has IIP3 of -9 dBm with FoM of 15.

scholarly journals Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

2017 ◽  
Vol 10 (1) ◽  
pp. 47-57
Author(s):  
Elena Sobotta ◽  
Guido Belfiore ◽  
Frank Ellinger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Dc Power ◽  
Active Inductors ◽  
Inductive Peaking ◽  
Noise Amplifier ◽  
28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

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