scholarly journals Ultra compact multi-standard low-noise amplifiers in 28 nm CMOS with inductive peaking

2017 ◽  
Vol 10 (1) ◽  
pp. 47-57
Author(s):  
Elena Sobotta ◽  
Guido Belfiore ◽  
Frank Ellinger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Bandwidth Enhancement ◽  
Dc Power ◽  
Active Inductors ◽  
Inductive Peaking ◽  
Noise Amplifier ◽  
28 Nm

This work presents the design of two compact multi-standard low-noise amplifier (LNA) in a 28 nm low-power bulk CMOS process. The transistor parameters were optimized by the gm/ID method taking into account the parasitics and the behavior of highly scaled transistors. To cover the industrial science medical (ISM)-bands around 2.4 and 5.8 GHz, the WLAN band as well as the Ku band a bandwidth enhancement is required. Two versions of LNAs, one with vertical inductors and one with active inductors, are implemented and verified by measurements. The noise figure (NF) exhibits 4.2 dB for the LNA with active inductors and 3.5 dB for the LNA with vertical inductors. The voltage gain reaches 12.8 and 13.4 dB, respectively, with a 3 dB-bandwidth of 20 GHz. Both input referred 1-dB-compression points are higher than −12 dBm making the chips attractive for communication standards with high linearity requirements. The chips consume 53 mW DC power and the LNA with active inductors occupies a core area of only 0.0018 mm2, whereas the version with vertical inductors requires 0.021 mm2.

Design of Low-Noise Two-Path Amplifier for 6–16 GHz Applications

2020 ◽  
pp. 2150136
Author(s):  
Asieh Parhizkar Tarighat ◽  
Mostafa Yargholi
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
High Gain ◽  
Low Noise ◽  
Cmos Process ◽  
Input Matching ◽  
Inductive Peaking ◽  
Linearity Improvement ◽  
Noise Amplifier ◽  
Path Structure

A two-path low-noise amplifier (LNA) is designed with TSMC 0.18[Formula: see text][Formula: see text]m standard RF CMOS process for 6–16[Formula: see text]GHz frequency band applications. The principle of a conventional resistive shunt feedback LNA is analyzed to demonstrate the trade-off between the noise figure (NF) and the input matching. To alleviate the mentioned issue for wideband application, this structure with noise canceling technique and linearity improvement are applied to a two-path structure. Flat and high gain is supplied by the primary path; while the input and output impedance matching are provided by the secondary path. The [Formula: see text][Formula: see text]dB bandwidth can be increased to a higher frequency by inductive peaking, which is used at the first stage of the two paths. Besides, by biasing the transistors at the threshold voltage, low power dissipation is achieved. The [Formula: see text][Formula: see text]dB gain bandwidth of the proposed LNA is 10[Formula: see text]GHz, while the maximum power gain of 13.1[Formula: see text]dB is attained. With this structure, minimum NF of 4.6[Formula: see text]dB and noise flatness of 1[Formula: see text]dB in the whole bandwidth can be achieved. The input impedance is matched, and S[Formula: see text] is lower than [Formula: see text]10 dB. With the proposed linearized LNA, the average IIP[Formula: see text][Formula: see text]dBm is gained, while it occupies 1051.7[Formula: see text][Formula: see text]m die area.

Low-power CMOS LNA based on dual resistive-feedback structure with peaking inductor for wideband application

2013 ◽  
Vol 5 (1) ◽  
pp. 65-70 ◽  
Author(s):  
Meng-Ting Hsu ◽  
Shih-Yu Hsu ◽  
Yu-Hwa Lin
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Output Stage ◽  
Chip Area ◽  
Inductive Peaking ◽  
Resistive Feedback ◽  
Low Power Cmos ◽  
Noise Amplifier

This paper presents a low-power and low-noise amplifier (LNA) with resistive-feedback configuration. The design consists of two resistive-feedback amplifiers. In order to reduce the chip area, a resistive-feedback inverter is adopted for input matching. The output stage adopts basic topology of an RC feedback for output matching, and adds two inductors for inductive peaking at the high band. The implemented LNA has a peak gain of 10.5 dB, the input reflection coefficient S11 is lower than −8 dB and the output reflection S22 is lower than −10.8 dB, and noise figure of 4.2–5.2 dB is between 1 and 10 GHz while consuming 12.65 mW from a 1.5 V supply. The chip area is only 0.69 mm2 and the figure of merit is 6.64 including the area estimation. The circuit was fabricated in a TSMC 0.18 um CMOS process.

scholarly journals CMOS low noise amplifiers for 1.575 GHz GPS applications

2009 ◽  
Vol 7 ◽  
pp. 145-150 ◽  
Author(s):  
M. Isikhan ◽  
A. Richter
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Performance Criteria ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Quality Factors ◽  
Voltage Range ◽  
Noise Amplifier ◽  
On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

scholarly journals Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-6 ◽  
Author(s):  
Ler Chun Lee ◽  
Abu Khari bin A'ain ◽  
Albert Victor Kordesch
Keyword(s):  
Noise Figure ◽  
Notch Filter ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Active Inductor ◽  
Cmos Process ◽  
Image Rejection ◽  
Fully Integrated ◽  
Active Inductors ◽  
Noise Amplifier

A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA) has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA). A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

scholarly journals Active Balun with Center-Tapped Inductor and Double-Balanced Gilbert Mixer for GNSS Applications

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1351
Author(s):  
Daniel Pietron ◽  
Tomasz Borejko ◽  
Witold Adam Pleskacz
Keyword(s):  
Phase Shift ◽  
Noise Figure ◽  
Low Noise ◽  
Global Navigation Satellite Systems ◽  
Cmos Process ◽  
Differential Signal ◽  
Satellite Systems ◽  
Active Balun ◽  
Noise Amplifier ◽  
Global Navigation Satellite

A new 1.575 GHz active balun with a classic double-balanced Gilbert mixer for global navigation satellite systems is proposed herein. A simple, low-noise amplifier architecture is used with a center-tapped inductor to generate a differential signal equal in amplitude and shifted in phase by 180°. The main advantage of the proposed circuit is that the phase shift between the outputs is always equal to 180°, with an accuracy of ±5°, and the gain difference between the balun outputs does not change by more than 1.5 dB. This phase shift and gain difference between the outputs are also preserved for all process corners, as well as temperature and voltage supply variations. In the balun design, a band calibration system based on a switchable capacitor bank is proposed. The balun and mixer were designed with a 110 nm CMOS process, consuming only a 2.24 mA current from a 1.5 V supply. The measured noise figure and conversion gain of the balun and mixer were, respectively, NF = 7.7 dB and GC = 25.8 dB in the band of interest.

A Highly-Integrated, Switchless and Baluns-Embedded Transceiver with a Differential Structure for C-Band Radar Application

2019 ◽  
Vol 29 (10) ◽  
pp. 2050160
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Zhennan Li ◽  
Zengqi Wang ◽  
Meng Zhang
Keyword(s):  
Output Power ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Image Rejection ◽  
Rf Switch ◽  
Differential Structure ◽  
Noise Amplifier ◽  
Image Rejection Ratio ◽  
Better Than

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

DC Power-Optimized Ka-Band GaN-on-Si Low-Noise Amplifier With 1.5 dB Noise Figure

2022 ◽  
pp. 1-4
Author(s):  
L. Pace ◽  
P. E. Longhi ◽  
W. Ciccognani ◽  
S. Colangeli ◽  
F. Vitulli ◽  
...  
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ka Band ◽  
Dc Power ◽  
Noise Amplifier ◽  
Gan On Si
Sign in / Sign up

Export Citation Format

Share Document