Multiple layers of silicon-on-insulator islands fabrication by selective epitaxial growth

1999 ◽  
Vol 20 (5) ◽  
pp. 194-196 ◽  
Author(s):  
Sangwoo Pae ◽  
Taichi Su ◽  
J.P. Denton ◽  
G.W. Neudeck
Author(s):  
Z. S. H. Weng-Sieh ◽  
J. C. Lou ◽  
W. G. Oldham ◽  
R. Gronsky

In the interest of obtaining increased integrated circuit device density, a relatively new technology known as selective epitaxial growth (SEG) of silicon is being explored, especially for improved isolation of devices including possible three dimensional (vertical) integration. This technology involves the deposition and selective nucleation and growth of silicon from the vapor phase, seeded by the silicon substrate. The process is “selective” because nucleation and growth occurs on the silicon substrate but is prohibited on the oxide. The epitaxial silicon proceeds to grow upward and laterally over the oxide.Silicon deposition was performed in a horizontal hot-walled low pressure chemical vapor deposition (LPCVD) reactor. A dry thermal oxide was grown on the substrates, patterned, and etched to create seed windows. A 900 °C prebake was performed at a pressure of 6 torr in a hydrogen ambient for a period of 15 minutes, with in some cases, a small concentration (approximately 0.025%) of dichlorosilane (DCS) gas, and deposition was performed at 850 °C through the decomposition of DCS gas: SiH2Cl2 -> Si(s)+ 2HCl(g).


1989 ◽  
Vol 65 (9) ◽  
pp. 3718-3721 ◽  
Author(s):  
D. A. Williams ◽  
R. A. McMahon ◽  
H. Ahmed ◽  
G. Garry ◽  
L. Karapiperis ◽  
...  

1987 ◽  
Vol 107 ◽  
Author(s):  
D.A. Williams ◽  
R.A. McMahon ◽  
H. Ahmed ◽  
L. Karapiperis ◽  
G. Garry ◽  
...  

AbstractThe effect of selective epitaxial growth (SEG) of silicon in the seed windows of silicon on insulator structures prior to recrystallization has been investigated. Subsequent zone melt recrystallization of these structures was performed in a dual electron beam system, and it was found that the full planarisation of the deposited silicon layer results in uniform film thickness after recrystallization. Cross sectional scanning and transmission electron microscopy, optical microscopy after defect etching, and bevelling are used to analyse the material. The SEG method improves the uniformity of the film for device island etching, and so is useful for all silicon on insulator applications, although the one of most interest for these investigations is the production of three dimensional circuitry. This is achieved by stacking layers of devices, and so planarity is particularly important.


1991 ◽  
Vol 238 ◽  
Author(s):  
Zara S. Weng ◽  
R. Gronsky ◽  
J. C. Lou ◽  
W. G. Oldham

ABSTRACTSilicon-on-insulator structures were formed by the selective epitaxial growth (SEG) of silicon and the epitaxial lateral overgrowth (ELO) of oxide shapes using an LPCVD hot-walled reactor at 850°C. The homoepitaxial interface changed character with modifications of the gas composition during the in-situ pre-epitaxial bake at 900°C. HREM images show ellipsoid-shaped inclusions lying along the homoepitaxial interface for silicon growth conducted with no dichlorosilane (DCS) flow during the prebake in H2. SIMS analysis indicates a large oxygen, fluorine, and carbon concentration at the interface. For structures grown with a small DCS flow in addition to H2 during the prebake, the homoepitaxial structural defects and the oxygen, fluorine, and carbon peaks are removed.


1992 ◽  
Vol 18 (3) ◽  
pp. 237-246 ◽  
Author(s):  
N. Afshar-Hanaii ◽  
J.M. Bonar ◽  
A.G.R. Evans ◽  
G.J. Parker ◽  
C.M.K. Starbuck ◽  
...  

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