High-speed decimation filter for delta-sigma analog-to-digital converter

1999 ◽  
Vol 9 (2) ◽  
pp. 3632-3635 ◽  
Author(s):  
Y.P. Xie ◽  
S.R. Whiteley ◽  
T. van Duzer
Keyword(s):  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Delta Sigma ◽  
Decimation Filter

scholarly journals High-Speed Superconductive Decimation Filter for Sigma-Delta Analog to Digital Converter

2017 ◽  
Vol 871 ◽  
pp. 012068
Author(s):  
Tomu Wakamatsu ◽  
Yuki Yamanashi ◽  
Nobuyuki Yoshikawa
Keyword(s):  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Decimation Filter

High Performance Analysis of CDS Delta-Sigma ADC in 45-Nanometer Regime

2014 ◽  
Vol 13 (01) ◽  
pp. 1450003
Author(s):  
Bhanupriya Bhargava ◽  
Pradeep Kumar Sharma ◽  
Shyam Akashe
Keyword(s):  
High Speed ◽  
Flicker Noise ◽  
Supply Voltage ◽  
Frequency Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Op Amp ◽  
Offset Voltage ◽  
Delta Sigma

In this paper, a correlated double sampling (CDS) technique is proposed in the design of a delta sigma analog-to-digital converter (ADC). These CDS techniques are very effective for the compensation of the nonidealities in switched-capacitor (SC) circuits, such as charge injection, clock feed-through, operational amplifier (op-amp) input-referred offset and finite op-amp gain. An improved compensation scheme is proposed to attain continuous compensation of clock feed-through and offset in SC integrators. Both high-speed and low-power operation is achieved without compromising the accuracy requirement. Also this CDS delta sigma ADC is the most promising circuit for analog to digital converter because this circuit reduces noise due to drift and low frequency noise such as flicker noise and offset voltage and also boosts the gain performance of the amplifier. Further, the simulation results of this circuit are verified on using a "cadence virtuoso tool" using spectre at 45 nm technology with supply voltage 0.7 V.

Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding

2011 ◽  
Vol 40 (5) ◽  
pp. 352-360 ◽  
Author(s):  
D. V. Morozov ◽  
M. M. Pilipko ◽  
A. S. Korotkov
Keyword(s):  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Data Encoding ◽  
Delta Sigma ◽  
Decimation Filter ◽  
Ternary Data

An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

2011 ◽  
Vol 32 (9) ◽  
pp. 095010 ◽  
Author(s):  
Zhengping Zhang ◽  
Yonglu Wang ◽  
Xingfa Huang ◽  
Xiaofeng Shen ◽  
Can Zhu ◽  
...  
Keyword(s):  
High Speed ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Ultra High Speed ◽  
Foreground Calibration

A High-Resolution and Low Offset Delta-Sigma Analog to Digital Converter for Detecting Photoplethysmography Signal

2021 ◽  
Author(s):  
Eka Fitrah Pribadi ◽  
Rajeev Kumar Pandey ◽  
Paul C.-P. Chao
Keyword(s):  
High Resolution ◽  
Continuous Time ◽  
Operational Amplifier ◽  
High Frequency ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Low Offset

Abstract A high-resolution, low offset delta-sigma analog to digital converter for detecting photoplethysmography (PPG) signal is presented in this study. The PPG signal is a bio-optical signal incorporated with heart functionality and located in the range of 0.1–10 Hz. The location to get PPG signal is on a pulsating artery. Thus the delta-sigma analog-to-digital (DS ADC) converter is designed specifically in that range. However, the DS ADC circuitry suffers from 1/f noise under 10 Hz frequency range. A chopper based operational amplifier is implemented in DS ADC to push the 1/f noise into high-frequency noise. The dc offset of the operational amplifier is also pushed to the high-frequency region. The DS ADC circuitry consists of a second-order continuous-time delta-sigma modulator. The delta-sigma modulator circuitry is designed and simulated using TSMC 180 nm technology. The continuous-time delta-sigma modulator active area layout is 746μm × 399 μm and fabricated using TSMC 180 nm technology. It operates in 100 Hz bandwidth and 4096 over-sampling ratios. The SFDR of the circuit is above 70 dB. The power consumption of the delta-sigma modulator is 35.61μW. The simulation is performed in three different kinds of corner, SS, TT, and FF corner, to guarantee the circuitry works in different conditions.

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