Some circuit design techniques for low-voltage analog functional elements using squaring circuits

In this paper, non-conventional circuit design techniques has been reviewed. The techniques discussed are widely used for realizing low voltage low power analog circuits. The discussed techniques in this paper are: Bulk Driven, Floating and Quasi-floating Gate followed by operating of Bulk Driven MOSFET in Floating and Quasi-floating Gate mode. In all the approach, the threshold voltage restriction is removed or reduced from the input signal path thereby reducing the power consumption. However, the adverse effect lies is terms of reduced performance parameters of MOSFET compared to conventional gate driven MOSFET parameters as shown in this paper through simulation results. The comparative analysis of MOSFET parameters results in encouragement of two approaches: Quasi-floating Gate and Bulk Driven Quasi-floating Gate MOSFET. Each of these approaches has its advantage in specific domains. Further in this paper, an Operational Transconductance Amplifier is proposed which use the Bulk Driven Quasi-floating Gate MOSFET technique and the same is amplifier under similar conditions is also realized using Bulk Driven MOSFET so as to highlight the advantage of Bulk Driven Quasi-floating Gate MOSFET over Bulk Driven MOSFET. All the performances metrics are achieved with the help of HSpice simulator using MOSFET models of 180nm technology provided by UMC.

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Low voltage analog circuit design techniques

IEEE Circuits and Systems Magazine ◽

10.1109/mcas.2002.999703 ◽

2002 ◽

Vol 2 (1) ◽

pp. 24-42 ◽

Cited By ~ 156

Author(s):

S.S. Rajput ◽

S.S. Jamuar

Keyword(s):

Circuit Design ◽

Analog Circuit ◽

Low Voltage ◽

Analog Circuit Design ◽

Design Techniques

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Low voltage circuit design techniques for voltage controlled oscillator

1997 1st International Conference, Control of Oscillations and Chaos Proceedings (Cat. No.97TH8329) ◽

10.1109/coc.1997.626668 ◽

2002 ◽

Author(s):

Chung Ming Yuen ◽

Kim Fung Tsang

Keyword(s):

Circuit Design ◽

Low Voltage ◽

Voltage Controlled Oscillator ◽

Design Techniques

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POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS

Journal of Circuits System and Computers ◽

10.1142/s0218126612400166 ◽

2012 ◽

Vol 21 (06) ◽

pp. 1240016 ◽

Cited By ~ 2

Author(s):

TORSTEN LEHMANN ◽

HOSUNG CHUN ◽

YUANYUAN YANG

Keyword(s):

Power Consumption ◽

Circuit Design ◽

Power Supply ◽

Integrated Circuit ◽

Power Efficiency ◽

Low Voltage ◽

Power Saving ◽

Design Approach ◽

Electrode Impedance ◽

Design Techniques

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.

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