POWER SAVING CIRCUIT DESIGN TECHNIQUES FOR IMPLANTABLE NEURO-STIMULATORS

2012 ◽  
Vol 21 (06) ◽  
pp. 1240016 ◽  
Author(s):  
TORSTEN LEHMANN ◽  
HOSUNG CHUN ◽  
YUANYUAN YANG
Keyword(s):  
Power Consumption ◽  
Circuit Design ◽  
Power Supply ◽  
Integrated Circuit ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Saving ◽  
Design Approach ◽  
Electrode Impedance ◽  
Design Techniques

Keeping power consumption low in implantable neuro-stimulators such as Cochlear Implants or Vision Prostheses is one of the major design challenges in their circuit design. Usually electrode impedance and stimulation currents required to elicit physiological responses mandates the use of large stimulation voltages, again dictating the use of high-voltage integrated circuit technologies. Power consumption in the stimulating circuits and associated supply generation circuits are the major contributors to overall system power dissipation. In this paper we present circuit design techniques that address power consumption in both stimulating circuits and power supply circuits. First, our power supply design approach is to recycle currents between the two low-voltage power supply needed for the stimulating circuits, whereby power consumption in these circuits can be close to halved. Second, our stimulating circuits design approach is to use very small quiescent currents, fast turn-on time and pre-stimulating dynamic calibration which allow the delivery of charge balanced bi-phasic stimulation pulses with very good power efficiency. A variation of this include passive charge recovery for further power reduction. In combination, significant implant power consumption reduction is achieved.

scholarly journals Toward Green Sensor Field by Optimizing Power Efficiency Using D-Policy M/G/1 Queuing Systems

2013 ◽  
Vol 9 (3) ◽  
pp. 241-260 ◽  
Author(s):  
Fuu-Cheng Jiang ◽  
Hsiang-Wei Wu ◽  
Fang-Yi Leu ◽  
Chao-Tung Yang
Keyword(s):  
Sensor Networks ◽  
Power Consumption ◽  
Power Efficiency ◽  
Ieee 802.15.4 ◽  
Power Saving ◽  
Rechargeable Batteries ◽  
Sensor Nodes ◽  
Traffic Load ◽  
Mathematical Framework ◽  
Sensor Field

Power efficiency is a crucially important issue in the IEEE 802.15.4/ZigBee sensor networks (ZSNs) for majority of sensor nodes equipped with non-rechargeable batteries. To increase the lifetime of sensor networks, each node must optimize power consumption as possible. Among open literatures, much research works have focused on how to optimally increase the probability of sleeping states using multifarious wake-up strategies. Making things different, in this article, we propose a novel optimization framework for alleviating power consumption of sensor node with the D-policy M/G/1 queuing approach. Toward green sensor field, the proposed power-saving technique can be applied to prolong the lifetime of ZSN economically and effectively. For the proposed data aggregation model, mathematical framework on performance measures has been formulated. Data simulation using MATLAB tool has been conducted for exploring the feasibility of the proposed approach. And also we analyze the average traffic load per node for tree-based ZSN. Focusing on ZigBee routers deployed at the innermost shell of ZSN, network simulation results validate that the proposed approach indeed provides a feasibly cost-effective approach for prolonging lifetime of ZSNs.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Low Voltage FGMOS Four Quadrants Analog Multiplier

2014 ◽  
Vol 918 ◽  
pp. 313-318
Author(s):  
Jesús de la Cruz-Alejo ◽  
L. Noe Oliva-Moreno
Keyword(s):  
Power Consumption ◽  
Power Supply ◽  
Low Voltage ◽  
Floating Gate ◽  
Cmos Process ◽  
Resistive Load ◽  
Analog Multiplier ◽  
Output Impedance ◽  
Cmos Transistors ◽  
Current Sensors

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

Low Power Electronics for Square-Wave Piezoactuator Driving

2009 ◽  
Author(s):  
G. Biancuzzi ◽  
T. Lemke ◽  
F. Goldschmidtboeing ◽  
O. Ruthmann ◽  
H.-J. Schrag ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Converter ◽  
Driving Voltage ◽  
Output Stage ◽  
Maximum Displacement ◽  
Artificial Sphincter ◽  
Charge Recovery

The German Artificial Sphincter System (GASS) project aims at the development of an implantable sphincter prosthesis driven by a micropump. During the last few years the feasibility of the concept has been proven. At present our team’s effort is focused on the compliance to safety regulations and on a very low power consumption of the system as a whole. Therefore a low-voltage multilayer piezoactuator has been developed to reduce the driving voltage of the micropump from approximately 300 Vpp to 40 Vpp. Doing so, the driving voltage is within the limits set by the regulations for active implants. The operation of the micropump at lower voltages, achieved using multilayer piezoactuators, has already resulted in a much better power efficiency. Nevertheless, in order to further reduce power consumption, we have also developed an innovative driving technique that we are going to describe and compare to other driving systems. A direct switching circuit has been developed where the buffer capacitor of the step-up converter has been replaced by the equivalent capacitance of the actuator itself. This avoids the switching of the buffer capacitor to the actuator, which would result in a very low efficiency. Usually, a piezoactuator needs a bipolar voltage drive to achieve maximum displacement. In our concept, the voltage inversion across the actuator is done using an h-bridge circuit, allowing the employment of one step-up converter only. The charge stored in the actuator is then partially recovered by means of a step-down converter which stores back the energy at the battery voltage level. The power consumption measurements of our concept are compared to a conventional driving output stage and also with inductive charge recovery circuits. In particular, the main advantage, compared to the latter systems, consists in the small inductors needed for the power converter. Other charge recovery techniques require very big inductors in order to have a significant power reduction with the capacitive loads we use in our application. With our design we will be able to achieve approximately 55% reduction in power consumption compared to the simplest conventional driver and 15% reduction compared to a charge recovery driver.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

1995 ◽  
Vol 30 (11) ◽  
pp. 1183-1188 ◽  
Author(s):  
T. Yamagata ◽  
S. Tomishima ◽  
M. Tsukude ◽  
T. Tsuruda ◽  
Y. Hashizume ◽  
...  
Keyword(s):  
Circuit Design ◽  
Low Voltage ◽  
Design Techniques

scholarly journals Different Types of Ultra-low Power Energy-Harvesting Design Techniques for IoT Applications

2019 ◽  
Vol 9 (1S5) ◽  
pp. 118-121
Keyword(s):  
Energy Harvesting ◽  
Power Consumption ◽  
Low Voltage ◽  
Threshold Level ◽  
Electronic Systems ◽  
Cmos Inverter ◽  
Switching Speed ◽  
Ultra Low Power ◽  
Level Shifter ◽  
Design Techniques

In this paper, different type of level shifter circuits, that can able to convert the sub-threshold level to superthreshold level signals are discussed. To develop the ultra- low static power consumption circuit designs such a way to switch on the transistor for a low voltage levels. To enhance the switching speed and minimize the dynamic power consumption, by incorporating the CMOS –inverter buffer circuit at the output side to improve the energy efficiently. These energy harvesting design techniques provides endless energy supply to electronic systems that are remotely located areas. More number of devices are controlled by IoT (Internet of Things) to perform the operation by remote sensing.

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