Hybrid H/sub 2//H/sub ∞/ estimation for phase-locked loop filter design

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations.

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Based on Phase-Locked Loop the ADF4350 Filter Design

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.631-632.301 ◽

2014 ◽

Vol 631-632 ◽

pp. 301-305 ◽

Cited By ~ 1

Author(s):

Bai Shan Zhao ◽

Ye Xu ◽

Jin Shuai Qu

Keyword(s):

Filter Design ◽

Structural Characteristics ◽

Circuit Simulation ◽

Phase Locked Loop ◽

Actual Situation ◽

Loop Filter ◽

Pass Filter ◽

Low Pass Filter ◽

Filter Structure ◽

Low Pass

Based on the basic principle of the phase locked loop, analyzes the structural characteristics of the loop filter technology and ADF4350; secondly, design and analysis of two order passive low pass filter, three order passive low pass filter, two order active low-pass filter, with parameters such as bandwidth, phase margin ADF4350 PLL, selection the loop filter is suitable for the actual situation; using ADIsimPLL software to determine the parameters and realize the optimization of S parameters on circuit simulation, optimized and then use ADS software to observe. Finally, according to the results of analysis to adapt to the situation three kinds of filter structure of ADF4350phase locked loop.

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Area efficient loop filter design for charge pump phase locked loop

Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 ◽

10.1145/1228784.1228823 ◽

2007 ◽

Author(s):

Raghavendra R G ◽

Bharadwaj Amrutur

Keyword(s):

Filter Design ◽

Charge Pump ◽

Phase Locked Loop ◽

Loop Filter ◽

Area Efficient

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Fuzzy logic for digital phase-locked loop filter design

IEEE Transactions on Fuzzy Systems ◽

10.1109/91.388174 ◽

1995 ◽

Vol 3 (2) ◽

pp. 211-218 ◽

Cited By ~ 41

Author(s):

D. Simon ◽

H. El-Sherief

Keyword(s):

Fuzzy Logic ◽

Filter Design ◽

Phase Locked Loop ◽

Loop Filter ◽

Digital Phase

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A phase-locked loop using ESO-based loop filter for grid-connected converter: performance analysis

Control Theory and Technology ◽

10.1007/s11768-021-00036-0 ◽

2021 ◽

Author(s):

Baoling Guo ◽

Seddik Bacha ◽

Mazen Alamir ◽

Julien Pouget

Keyword(s):

Performance Analysis ◽

Frequency Domain ◽

Low Frequency ◽

Experimental Tests ◽

Frequency Measurement ◽

Phase Locked Loop ◽

Frequency Domain Analysis ◽

Loop Filter ◽

Control Stability ◽

Unbalanced Grid

AbstractAn extended state observer (ESO)-based loop filter is designed for the phase-locked loop (PLL) involved in a disturbed grid-connected converter (GcC). This ESO-based design enhances the performances and robustness of the PLL, and, therefore, improves control performances of the disturbed GcCs. Besides, the ESO-based LF can be applied to PLLs with extra filters for abnormal grid conditions. The unbalanced grid is particularly taken into account for the performance analysis. A tuning approach based on the well-designed PI controller is discussed, which results in a fair comparison with conventional PI-type PLLs. The frequency domain properties are quantitatively analysed with respect to the control stability and the noises rejection. The frequency domain analysis and simulation results suggest that the performances of the generated ESO-based controllers are comparable to those of the PI control at low frequency, while have better ability to attenuate high-frequency measurement noises. The phase margin decreases slightly, but remains acceptable. Finally, experimental tests are conducted with a hybrid power hardware-in-the-loop benchmark, in which balanced/unbalanced cases are both explored. The obtained results prove the effectiveness of ESO-based PLLs when applied to the disturbed GcC.

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