A robust high-speed and low-power CMOS current comparator circuit

Author(s):  
Lu Chen ◽  
Bingxue Shi ◽  
Chun Lu

Author(s):  
Soheil Ziabakhsh ◽  
Hosein Alavi Rad ◽  
Alireza Saberkari ◽  
Shahriar Baradaran Shokouhi




Author(s):  
GOPALA KRISHNA.M ◽  
UMA SANKAR.CH ◽  
NEELIMA. S ◽  
KOTESWARA RAO.P

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.





2001 ◽  
Vol 36 (8) ◽  
pp. 1250-1262 ◽  
Author(s):  
Jinn-Shyan Wang ◽  
Ching-Rong Chang ◽  
Chingwei Yeh


2008 ◽  
Vol 44 (3) ◽  
pp. 171 ◽  
Author(s):  
D. Banks ◽  
C. Toumazou


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