A Low Power SAR ADC with Digital Error Correction Technique for Wearable and Implantable ECG Devices

Aims: To propose an 8-bit differential input low power successive approximation register (SAR) ADC with digital error correction technique for sensing bio-potential signals in wearable and implantable devices. Background: As Dynamic comparators have the advantages of full swing output, low power consumption, high speed, and high impedance at the input, they are preferably used in energy efficient SAR ADC’s. But since dynamic comparator is the most frequently used block in SAR ADC, research is ongoing to furthermore reduce its µW power. Also, as offset voltage of comparator affects the linearity of ADC, it must be minimized. Linearity can further be improved by calibrating the output of ADC and extensive survey on the calibration methods prove that addition only digital error correction method is efficient in terms of power. Objective: To design a low power and low offset dynamic comparator intended for SAR ADC to achieve highly linear digital output. In addition to this, to implement a power efficient digital error correction technique for the output of SAR ADC to overcome the non-idealities due to process variations. Method: As power consumption is proportional to the number of transistors, proposed comparator is a design obtaining same output as the existing dynamic comparators with reduced transistor count. The proposed comparator along with low power full swing three input XOR logic gate is implemented in SAR ADC with digital error correction technique in cadence 45 nm technology files and its performance parameters are simulated. Result: The layout of the proposed dynamic comparator occupies an area of 3 µm2. The simulation results of this comparator with a load of 1 pF show that it has a total offset of 11.2 mV, delay of 0.9 ns and power consumption of 24 nW. It also achieves a gain of 49.5 i.e 33.86 dB. The 8-bit ADC along with digital error correction technique operating at 143-kS/s and under 0.6 V supply voltage simulated in 45nm technology consumes only 0.12 µW power. The DNL and INL error obtained are +0.22/-0.2 LSB and -0.28 LSB respectively. SNR limited by noise is 48.25 dB, SFDR is 48.64 dB and ENOB achieved is 7.72. Conclusion: To satisfy the requirement of the wearable and implantable devices a low power SAR ADC with good linearity is designed using low power and low offset dynamic comparator. A digital error correction technique using low power XOR logic gate is implemented at the SAR ADC output to minimize the non idealities due to the process variations.

Low-power latch comparator with accurate hysteresis control

Recent research has focused on finding ways to control hysteresis of dynamic comparators. The current proposed techniques are based on either geometrical dimension adjustment or digital control. The first case does not allow for post fabrication control, while the second has limited accuracy. This paper presents a new dynamic comparator design with external hysteresis adjustment using an analog voltage. This is achieved by proposing an architecture including control devices with a specific sizing. This is performed with no significant increase of the design complexity, keeping the power consumption as low as possible. The design is analyzed, showing that the proposed solution allows accurate hysteresis adjustment without affecting the inherent circuit properties. The dynamic comparator is also implemented using a 180 nm commercially available CMOS technology. The results show that a variation of 550 mV of the control voltage allows an accurate hysteresis adjustment ranging from 0 to 40 mV, according to the input conditions. Moreover, the simplicity of the circuit in conjunction with the use of dynamic technology have allowed the best performances to be achieved compared to the current state of the art, in terms of energy with an FoM equal to 116 fJ/decision and silicon area of 180 µm2 .

Analysis of Low Power Dynamic Comparator

Low power consumption, high performance dynamic comparators are widely used in high-speed Analog to Digital Converters (ADCs) and advanced input/output circuits. Mostly unique comparators utilize the latching stage thorough cross-coupled inverters, which gives a solid positive feedback, to fasten the comparison and reduce the static- power dissipation. In this paper, the analysis of dynamic comparators having best performance parameters in terms of power dissipation is presented. This is achieved by adopting low power techniques like adding transistors and sizing them to get efficient circuit. The proposed circuits are able to reduce power dissipation from 40-50%