A spread spectrum clock generator with phase-rotation algorithm for 6Gbps clock and data recovery

Author(s):  
Chi-Hsien Lin ◽  
Yen-Ying Huang ◽  
Shu-Rung Li ◽  
Yuan-Pu Cheng ◽  
Shyh-Jye Jou
Author(s):  
Vijayalakshmi S ◽  
Nagarajan V

In this work, the communication of a channel in the human body has a characteristic (time-domain) which can be measured at various distances in transmission and various frequencies of a signal by the printed circuit board-an analog frontend board (PCB-AFE) support. Besides, for the wideband signal of Body Channel Communication (BCC), a human body skin acts within a range of 1 Mb/s to 40 Mb/s as the transmission medium. This communication is more stable and attenuating low power while comparing with all another transmission medium in wireless. Moreover, due to the motion of a human body, this communication doesn't get affected. Though, the body antenna gives effects in the communication of a channel of the human body by occurs some interference. The Manchester data acts as encoder and decoder in transmitter and receiver parts respectively, in an AFE-PCB the Manchester encoder data is amplified after receiving the data from end to end channel of a human body. The data quality is improved by 7X sampler in clock data recovery (CDR) circuit. Therefore, the proposed design of reliable BCC Transceiver with SSCG and PNR Generator is processed in XilinxISE14.5, ModelSim Simulator 6.5a (Quartus II 8.1), and Micro wind software tools. It is also implemented in a XilinxXC9572XL kit. The power consumption and delay is reduced up to 90%, speed is increased up to 50% and leakage current is reduced up to 80% in the transmitter part.


2006 ◽  
Vol 4 ◽  
pp. 287-291
Author(s):  
S. Tontisirin ◽  
R. Tielert

Abstract. A Gb/s clock and data recovery (CDR) circuit using 1/4th-rate digital quadricorrelator frequency detector and skew-calibrated multi-phase voltage-controlled oscillator is presented. With 1/4th-rate clock architecture, the coil-free oscillator can have lower operation frequency providing sufficient low-jitter operation. Moreover, it is an inherent 1-to-4 DEMUX. The skew calibration scheme is applied to reduce phase offset in multi-phase clock generator. The CDR with frequency detector can have small loop bandwidth, wide pull-in range and can operate without the need for a local reference clock. This 1/4th-rate CDR is implemented in standard 0.18 μm CMOS technology. It has an active area of 0.7 mm2 and consumes 100 mW at 1.8 V supply. The CDR has low jitter operation in a wide frequency range from 1–2.25 Gb/s. Measurement of Bit-Error Rate is less than 10−12 for 2.25 Gb/s incoming data 27−1 PRBS, jitter peak-to-peak of 0.7 unit interval (UI) modulation at 10 MHz.


Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.


2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  

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