Charge Based Power Side-Channel Attack Methodology for an Adiabatic Cipher

SIMON is a block cipher developed to provide flexible security options for lightweight hardware applications such as the Internet-of-things (IoT). Safeguarding such resource-constrained hardware from side-channel attacks poses a significant challenge. Adiabatic circuit operation has recently received attention for such applications due to ultra-low power consumption. In this work, a charge-based methodology is developed to mount a correlation power analysis (CPA) based side-channel attack to an adiabatic SIMON core. The charge-based method significantly reduces the attack complexity by reducing the required number of power samples by two orders of magnitude. The CPA results demonstrate that the required measurements-to-disclosure (MTD) to retrieve the secret key of an adiabatic SIMON core is 4× higher compared to a conventional static CMOS based implementation. The effect of increase in the target signal load capacitance on the MTD is also investigated. It is observed that the MTD can be reduced by half if the load driven by the target signal is increased by 2× for an adiabatic SIMON, and by 5× for a static CMOS based SIMON. This sensitivity to target signal capacitance of the adiabatic SIMON can pose a serious concern by facilitating a more efficient CPA attack.

Design and Implementation of Low-Power, High-Performance 2-4- and 4-16-Line Decoders using Adiabatic Logic Circuits

In the present emerging field for the research, the reduction of power has become a major design problem in VLSI technology. As the size of the system shrinking gradually it has become the one the prime concerns in the design of decoders. The main purpose of this paper is to minimize the power and delay capabilities comparison with ordinary CMOS design. To avoid power reduction by introducing a different technique. In this paper we are approaching the adiabatic circuit has been introduced. The power dissipation in the adiabatic circuits can be minimized when compared to conventional CMOS logic. The designing of decoders with the adiabatic logic can reduce the power average power by 10.80% and delay by 21%, 23% and 24% at different voltage levels compared to the conventional CMOS. Finally, Spice simulation results show the comparison results between the existing CMOS decoders and the proposed adiabatic logic-based decoders at 32nm technology in all cases.

An Adiabatic Circuit with Consecutive Changes of the Duty Ratio of the Switching Transistor Using a Microprocessor

A circuit for adiabatically charging and discharging a supercapacitor was designed. A microprocessor sets the duty ratio of the switching transistors that control the inductor current. Changing the duty ratio in a stepwise fashion causes the output voltage to change in a similar fashion. Stepwise voltage changes enable adiabatic charging and discharging. Current measurements showed that the eight-step charging and discharging of a supercapacitor reduced the energy dissipation to one-eighth of that for a constant-voltage process. The circuit enables precise voltage control in small steps.

Low Power VLSI Circuit Design using Energy Recovery Techniques

With the rapidly evolving silicon technology, the power density becomes increasingly high. Quadratically related to power, the voltage scaling offers a means of minimizing energy. However, power supply scaling demands less threshold voltage, which rises leakage current. Several low power techniques have been devised. This chapter deals with the non-conventional low power design solutions, based on adiabatic switching theory. In such circuits, the energy rather than getting dissipated during every cycle, is transferred back and forth between the logic and power-clock sources. A brief discussion on the reversible logic circuits will be presented followed by the fully adiabatic and quasi-adiabatic circuits. The use of power-clock sources for operating the adiabatic circuits will also be introduced. The generalized energetics of an adiabatic circuit followed by the typical loss models of the adiabatic families are presented. Some of the adiabatic circuits employing CMOS transistors are introduced in the chapter. A short comparison for the adiabatic circuit leakage models follows.

ENERGY ESTIMATION FOR n-INPUT ADIABATIC LOGIC GATE: A PROPOSED ANALYTICAL MODEL

In this paper, an analytical model is proposed to estimate the energy consumption of n-input adiabatic logic gate. The model is based on RC linearization of the adiabatic circuit network. To validate the model expressions, simulations are carried out at 90 nm technology node using the Cadence Spectre simulator. Model validates with simulation results at a maximum error equals to 9.94%. Model expressions are also applied in comparison of energy performance of adiabatic logic and conventional CMOS logic. Proposed research work suggests the operating conditions which makes the adiabatic logic more energy efficient than conventional CMOS logic.

DFAL: Diode-Free Adiabatic Logic Circuits

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.