A sub-1v low-dropout regulator with an on-chip voltage reference

2008 ◽  
Author(s):  
Wei-Jen Huang ◽  
Shen-Iuan Liu
Keyword(s):  
Voltage Reference ◽  
Low Dropout Regulator ◽  
On Chip

An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

2017 ◽  
Vol 26 (10) ◽  
pp. 1750146
Author(s):  
Suresh Alapati ◽  
Sreehari Rao Patri ◽  
K. S. R. Krishna Prasad
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Transient Performance ◽  
Linear Regulator ◽  
Current Change ◽  
Load Regulation ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Fast Rise ◽  
Fixed Bias

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.

Parameter optimization of an on-chip voltage reference circuit using evolutionary programming

2001 ◽  
Vol 5 (4) ◽  
pp. 414-421 ◽  
Author(s):  
Dongkyung Nam ◽  
Yun Deuk Seo ◽  
Lae-Jeong Park ◽  
Cheol Hoon Park ◽  
Burnsup Kim
Keyword(s):  
Parameter Optimization ◽  
Evolutionary Programming ◽  
Voltage Reference ◽  
Reference Circuit ◽  
On Chip

scholarly journals CAPACITOR-LESS LOW-DROPOUT VOLTAGE REGULATOR

2014 ◽  
pp. 50-55
Author(s):  
SRIRANGANATHA SAGAR.K.N ◽  
POORNIMA N. ◽  
VIJAYA KUMAR. V
Keyword(s):  
Output Voltage ◽  
Total Error ◽  
Cmos Technology ◽  
Damping Factor ◽  
Frequency Compensation ◽  
Load Variations ◽  
Power Supply Rejection Ratio ◽  
Control Frequency ◽  
Low Dropout Regulator ◽  
On Chip

A 1.2-V 40-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitorfree operation. The proposed LDO has been implemented in a tsmc65nm CMOS technology, and the total error of the output voltage due to line and load variations is less. Moreover, the output voltage can recover with ≈2.3μs for full load current changes. The power-supply rejection ratio at 1 MHz is 26 dB.

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