An Adaptively Biased Capacitor-Less Low Dropout Regulator with Improved Transient Performance

2017 ◽  
Vol 26 (10) ◽  
pp. 1750146
Author(s):  
Suresh Alapati ◽  
Sreehari Rao Patri ◽  
K. S. R. Krishna Prasad
Keyword(s):  
Supply Voltage ◽  
Cmos Process ◽  
Transient Performance ◽  
Linear Regulator ◽  
Current Change ◽  
Load Regulation ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Fast Rise ◽  
Fixed Bias

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6[Formula: see text]V, dropout voltage of 200[Formula: see text]mV and a quiescent current of 64.4[Formula: see text][Formula: see text]A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95[Formula: see text]mV for a load current changes from 0[Formula: see text]mA to 100[Formula: see text]mA and an overshoot of 150.1[Formula: see text]mV for a current change of 100–0[Formula: see text]mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6[Formula: see text][Formula: see text]V/mA and power supply rejection (PSR) of [Formula: see text]47.8[Formula: see text]dB@ 10[Formula: see text]kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180[Formula: see text]nm UMC CMOS process is employed.

A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340024
Author(s):  
HAO LUO ◽  
YAN HAN ◽  
RAY C. C. CHEUNG ◽  
TIANLIN CAO ◽  
XIAOPENG LIU ◽  
...  
Keyword(s):  
High Resolution ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Process ◽  
Signal To Noise ◽  
Dc Gain ◽  
Micro Power ◽  
Class C ◽  
On Chip ◽  
Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

2015 ◽  
Vol 25 (01) ◽  
pp. 1640006
Author(s):  
Suyan Fan ◽  
Man-Kay Law ◽  
Mingzhong Li ◽  
Zhiyuan Chen ◽  
Chio-In Ieong ◽  
...  
Keyword(s):  
Solar Cell ◽  
Power Consumption ◽  
Supply Voltage ◽  
Capacitive Sensor ◽  
Cmos Process ◽  
Readout Circuit ◽  
Worst Case ◽  
Average Power Consumption ◽  
Input Range ◽  
On Chip

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

scholarly journals A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1042
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Yajun Xia ◽  
Niansong Mei
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Dual Mode ◽  
Operating Modes ◽  
On Chip

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

A low power trimming-free CMOS relaxation oscillator with process and temperature compensation

2020 ◽  
Vol 34 (16) ◽  
pp. 2050176
Author(s):  
Yao Wang ◽  
Mengmeng Yao ◽  
Zhaolei Wu ◽  
Lijun Sun ◽  
Juin Jei Liou
Keyword(s):  
Temperature Compensation ◽  
Supply Voltage ◽  
Relaxation Oscillator ◽  
Oscillation Period ◽  
Frequency Variation ◽  
Cmos Process ◽  
Temperature Variations ◽  
Simulated Temperature ◽  
On Chip ◽  
Rc Time Constant

The design of a 22 KHz 358 nW CMOS relaxation oscillator with a process and temperature compensation scheme is presented. Instead of the commonly used RC time constant, the oscillation period of the proposed circuit is determined by the resistance ratio of several resistors, which is insensitive to process and temperature variations. The on-chip relaxation oscillator is simulated in a 0.18 [Formula: see text]m CMOS process. Without any calibration or off-chip components, the frequency variation of the proposed oscillator is ±[Formula: see text]3.24% across [Formula: see text] to 100[Formula: see text]C temperature range and 5 different process corners. Compared to the conventional relaxation oscillator, the frequency variation of this circuit is reduced by 89%. The simulated temperature coefficient is 111 ppm/[Formula: see text]C, and the frequency variation over the supply voltage from 1.2 V to 1.7 V is 2.1%/V. The typical power consumption of the proposed circuit is 358 nW.

Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications

2019 ◽  
Vol 28 (03) ◽  
pp. 1950043 ◽  
Author(s):  
M. Jahangiri ◽  
A. Farrokhi
Keyword(s):  
Output Voltage ◽  
Input Voltage ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Wide Range ◽  
Unity Gain ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Voltage Spike

A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50[Formula: see text]mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The output voltage of the LDO was set to 1.2[Formula: see text]V for an input voltage of 1.4–2[Formula: see text]V. The Simulation results verify that the transient times are less than 2.8[Formula: see text][Formula: see text]s and the maximum undershoot and overshoot are 20[Formula: see text]mV while consuming only 26[Formula: see text][Formula: see text]A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100[Formula: see text]PF.

Low-Power Passive/Active UHF RFID Tag Transceiver with Frequency Locked On-chip Oscillator

2020 ◽  
Vol 29 (14) ◽  
pp. 2050234 ◽  
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Niansong Mei
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Operating Mode ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Passive Mode ◽  
Rfid Tag ◽  
Active Mode ◽  
Frequency Identification ◽  
On Chip

A reconfigurable architecture is presented to be compatible with conventional passive operating mode and active mode for ultrahigh frequency (UHF) and radio-frequency identification (RFID) tag. The transceiver with frequency locked on-chip oscillator is proposed to increase the read range of RFID system and the lifetime of tag. The transceiver is fabricated in 0.18[Formula: see text][Formula: see text]m standard CMOS process with the active area of 0.246[Formula: see text]mm2. For passive mode, the sensitivity of tag is [Formula: see text][Formula: see text]dBm. For the active mode, the sensitivity is [Formula: see text][Formula: see text]dBm only consuming 1.2[Formula: see text][Formula: see text]W under the supply voltage of 0.8[Formula: see text]V. The output power is [Formula: see text][Formula: see text]dBm for active transmitting mode and the power consumption is 450[Formula: see text][Formula: see text]W under the supply voltage of 1[Formula: see text]V.

Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000820-000824 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Wen Cheng Lai ◽  
Yong-Jhen Jiangn
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Third Order ◽  
Chip Design ◽  
Chip Area ◽  
Rf Receiver ◽  
Front End ◽  
On Chip

An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of −24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17–5.98 GHz and phase noise of −118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 × 1.2 mm2.

scholarly journals CMOS low noise amplifiers for 1.575 GHz GPS applications

2009 ◽  
Vol 7 ◽  
pp. 145-150 ◽  
Author(s):  
M. Isikhan ◽  
A. Richter
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Performance Criteria ◽  
Low Noise Amplifiers ◽  
Cmos Process ◽  
Quality Factors ◽  
Voltage Range ◽  
Noise Amplifier ◽  
On Chip

Abstract. This paper presents Low Noise Amplifier (LNA) versions designed for 1.575 GHz L1 Band Global Positioning System (GPS) applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF) of 1.5 dB. Input referred 1 dB compression point (ICP) is measured as −5.5 dBm and −10 dBm for different versions.

Sign in / Sign up

Export Citation Format

Share Document