scholarly journals Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

2014 ◽  
Vol 8 (1) ◽  
pp. 77-83
Author(s):  
Pan Zhongliang ◽  
Chen Ling ◽  
Chen Yihui
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Circuits ◽  
Test Pattern ◽  
Average Power ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Delay Faults ◽  
High Power Consumption ◽  
Test Vectors

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

scholarly journals An Efficient Test Pattern Generation Scheme for an On Chip BIST

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 551-562 ◽  
Author(s):  
B. K. S. V. L. Varaprasad ◽  
L. M. Patnaik ◽  
H. S. Jamadagni ◽  
V. K. Agrawal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Pattern ◽  
Circuit Simulation ◽  
Cost Effective ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Space Applications ◽  
Efficient Test ◽  
On Chip

Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

A low power test pattern generation for built-in self-test based circuits

2011 ◽  
Vol 98 (3) ◽  
pp. 301-309 ◽  
Author(s):  
Bo Ye ◽  
Tianwang Li ◽  
Qian Zhao ◽  
Duo Zhou ◽  
Xiaohua Wang ◽  
...  
Keyword(s):  
Low Power ◽  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Power Test ◽  
Low Power Test ◽  
Self Test ◽  
Built In Self Test
Sign in / Sign up

Export Citation Format

Share Document