The existing fault models like stuck-at, small delay defect, transition, and bridge fault models and their associated patterns are becoming less efficient, as the technology moves to increasingly smaller geometries. It is because traditional defect models target the faults only on IC gate boundaries, and the interconnects between the cells, but a significant population of defects (perhaps up to 50%) occurs within the cells or gates which are not specifically targeted by existing ATPG fault models. In this paper, a new ATPG methodology known as the Cell-aware test is implemented explicitly to target the defects caused by cell-internal open and short faults and improve the manufacturing test quality by minimizing the test escapes. This work explains how a Cell-Aware ATPG method performs a characterization on the GDSII data of library cell`s to produce a CAT library view (UDFM), test Pattern generation, and comparison between Traditional and Cell-Aware ATPG. The Cell-Aware ATPG is implemented using Tessent Testkompress, traditional ATPG is also developed to study and analyze both ATPG methodologies comparatively. Experiment results show a significant improvement in faults being targeted at an expense of an increase in pattern count and run-time. Obtained 71.28% and 59.38% test coverage for UDFM static and UDFM delay respectively. Achieved significant improvement in the test escapes with Cell-Aware Patterns when compared to traditional ATPG patterns.
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects
