A low power quadrature and divide-by-two frequency VCO design mixer with charge-injection for biomedical applications

Author(s):  
Wen-Cheng Lai ◽  
Jhin-Fang Huang ◽  
Pi-Gi Yang ◽  
Chien-Ming Hsu ◽  
Kuo-Lung Chen
2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.


Author(s):  
Meng Fu ◽  
Stan Skafidas ◽  
Iven Mareels

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.


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