A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications

2018 ◽  
Vol 10 (3) ◽  
pp. 21-32
Author(s):  
Meng Fu ◽  
Stan Skafidas ◽  
Iven Mareels
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Signal To Noise Ratio ◽  
Electronic Devices ◽  
Silicon Area ◽  
Novel Structure ◽  
Channel Bandwidth ◽  
Shift Keying ◽  
Mics Band ◽  
Demodulation Method

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.

A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications

2020 ◽  
pp. 852-864
Author(s):  
Meng Fu ◽  
Stan Skafidas ◽  
Iven Mareels
Keyword(s):  
Low Power ◽  
Bit Error Rate ◽  
Signal To Noise Ratio ◽  
Silicon Area ◽  
Awgn Channel ◽  
Novel Structure ◽  
Channel Bandwidth ◽  
Shift Keying ◽  
Mics Band ◽  
Demodulation Method

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.

The Application of DFT Technology in Soft Demodulation of π/4-DQPSK Signals

2014 ◽  
Vol 644-650 ◽  
pp. 4439-4442
Author(s):  
Yan Jun Wu ◽  
Gang Fu ◽  
Peng Yu
Keyword(s):  
Simple Structure ◽  
Signal To Noise Ratio ◽  
Software Radio ◽  
Stable Region ◽  
Sampling Point ◽  
Receiver Design ◽  
Phase Shift Keying ◽  
Soft Demodulation ◽  
Shift Keying ◽  
Demodulation Method

Presented to the π / 4 differential quaternary phase shift keying signal (π/4-DQPSK) using the discrete Fourier transform (DFT) for software demodulation algorithm in consideration of the actual received waveform into transition to π/4-DQPSK District and stable region, and only the waveform sampling point DFT transform the region stable recovery decision. simulation gives the demodulation method to achieve the same differential demodulation relatively simple structure, and the anti-noise in the signal to noise ratio greater than 3dB better performance than the differential demodulation performance, expected the algorithm is applied π/4-DQPSK software radio receiver design.

scholarly journals Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
M. F. Siddiqui ◽  
A. W. Reza ◽  
J. Kanesan ◽  
H. Ramiah
Keyword(s):  
Low Power ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Research Work ◽  
Coefficient Matrix ◽  
Silicon Area ◽  
Pipelined Architecture ◽  
Common Subexpression Elimination ◽  
Cost Metrics ◽  
Area Efficient

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

Transmission of Binary Information with a Chaos Coded Communication System using QDPSK-Modulation

1998 ◽  
Vol 53 (12) ◽  
pp. 1022-1028
Author(s):  
Andreas Magauer ◽  
Soumitro Banerjee
Keyword(s):  
Communication System ◽  
Secure Communication ◽  
Signal To Noise Ratio ◽  
Chaotic Oscillator ◽  
Bandwidth Efficiency ◽  
Phase Shift Keying ◽  
Channel Bandwidth ◽  
Shift Keying ◽  
Binary Information ◽  
Coded Communication

Abstract Synchronisation of chaotic oscillators offers a way of practical application of the theory of Chaos in obtaining secure communication. In this work we introduce a nonautonomous chaotic system with sinusoidal external force for communication of binary signals. The information is applied to the phase position of the sinusoidal forcing signal of the chaotic oscillator using a quadrature difference phase shift keying (QDPSK) modulation. An inverse synchronisation system approach with direct modulation is applied. We describe the system in detail and discuss the requirements of a secure communication system. Issues related to bit error rate, transfer rate, signal to noise ratio, channel bandwidth, bandwidth efficiency and channel capacity are discussed, and the properties of the realized communication system are placed in relation to the requirements of a secure communication system.

A Novel FSK Generator Using a Second Generation Current Controlled Conveyor

2020 ◽  
Vol 10 (6) ◽  
pp. 902-908
Author(s):  
Syed Zahiruddin ◽  
Avireni Srinivasulu ◽  
Musala Sarada
Keyword(s):  
Biomedical Applications ◽  
Second Generation ◽  
Current Mode ◽  
Enabling Technology ◽  
Active Device ◽  
Passive Components ◽  
Existing Structures ◽  
Generator Circuit ◽  
Shift Keying ◽  
The Times

Objective: The interest concern towards the development of enabling technology towards new current mode devices has forced the designers and researchers for the invention of devices, which has having the characteristics like such as low power, robustness, compactness, efficiency and scalability. Methods: Second Generation Current Controlled Conveyor (CCCII) is the prevailing current mode device of the times today. Since its invention by A. Fabre, it has prominent applications in the field of analog signal processing and in biomedical applications too. In this manuscript, CCCII is used as an enabling device to design a Frequency Shift Keying (FSK) Generator. Results: The proposed topology is designed using a single active device CCCII with least passive components. The circuit enjoys the features of like electronic tunability of frequency using the bias current. Conclusion: It can be concluded that the FSK generator circuit designed using single CCCII confers better results in contrast to the existing structures. The maximum power consumption is 0.196 mW. The proposed circuit has the benefit of simple configuration, which is very much proficient for IC fabrication.

A Novel Symbol Rate Estimation Algorithm for Phase Modulating Signals in Wireless Communications

2013 ◽  
Vol 443 ◽  
pp. 392-396
Author(s):  
Peng Zhou ◽  
Chi Sheng Li
Keyword(s):  
Signal To Noise Ratio ◽  
Estimation Algorithm ◽  
Frequency Resolution ◽  
Phase Shift Keying ◽  
Phase Jump ◽  
Rate Estimation ◽  
Awgn Channel ◽  
Symbol Rate ◽  
Shift Keying ◽  
Simulation Results

In this paper, we proposed a new symbol rate estimation algorithm for phase shift keying (PSK) and qua drawtube amplitude modulation (QAM) signals in AWGN channel First we constructe a delay-multiplied signal, from which we obtaine the modulated information. Then we calculated the instantaneous autocorrelation of the delay-multiplied signal to pick out the phase jump. To eliminate the restriction of frequency resolution in fast Fourier transform, we performed a Chirp-Z transform to find out the exact spectral line which represente the symbol rate of the signal to be analyzed. Compared with the existing algorithms, it is a simple solution that has a better performance and accuracy in low signal-to-noise-ratio channel conditions. Simulation results show that the probability of relative estimating deviation below 0.1% reaches 100% and the average and standard variance of absolute estimation deviation are at the magnitude of 10-2 when SNR is over 2dB.

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